Jeffrey Daniel Potter

US Patent:

6433790, Aug 13, 2002

Filed:

Jan 19, 1999

Appl. No.:

09/234133

Inventors:

Ralph Clayton Taylor - Deland FL
Daniel B. Clifton - Rockledge FL
David Gotwalt - Los Gatos CA
Michael A. Mang - Oviedo FL
Thomas A. Piazza - Granite Bay CA
Jeffrey D. Potter - Winter Springs FL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 536

US Classification:

345611, 345606, 345441

Abstract:

A method and system for rendering a feature, such as a line, for display on an array of pixels. With this method, the line is identified on the pixel array, the line is expanded into a polygon, and color values are determined for the pixels within the polygon. Also, an antialiasing region is identified in the polygon, and blend values are computed for the pixels in this antialiasing region. Then, the color values determined for the pixels in the antialiasing region are modified as a function of these computed blend values. The pixels in the antialiasing region may then be shown at their modified color values, while the pixels that are in the polygon but not in the antialising region may be shown at their original determined color value. Preferably, the blend values for the pixels in the antialiasing region are calculated as a function of the locations of the pixels in that region. For example, the blend value for each of these pixels may be calculated as a function of four values, each one representing the Manhattan distance from the pixel to a respective one of the edges of the polygon.

US Patent:

7050063, May 23, 2006

Filed:

Feb 11, 2000

Appl. No.:

09/502994

Inventors:

Michael Mantor - Orlando FL, US
John Austin Carey - Winter Springs FL, US
Ralph Clayton Taylor - Deland FL, US
Thomas A. Piazza - Granite Bay CA, US
Jeffrey D. Potter - Winter Springs FL, US
Angel E. Socarras - Lake Mary FL, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G09G 5/00

US Classification:

345582, 345552, 345557, 345558, 345535, 345564, 345565

Abstract:

A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized.

US Patent:

20060164429, Jul 27, 2006

Filed:

Jan 30, 2006

Appl. No.:

11/344030

Inventors:

Michael Mantor - Orlando FL, US
John Carey - Winter Springs FL, US
Ralph Taylor - Deland FL, US
Thomas Piazza - Granite Bay CA, US
Jeffrey Potter - Winter Springs FL, US
Angel Socarras - Lake Mary FL, US

International Classification:

G09G 5/00

US Classification:

345582000

Abstract:

A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm. By labeling the texture map blocks (double quad words), a partitioning scheme is developed which allow the cache controller structure to be very modular and easily realized. The texture cache arbiter is used for scheduling and controlling the actual transfer of texels from the texture main memory into the texture cache memory and controlling the outputting of texels for each pixel to an interpolating filter from the cache memory.

US Patent:

52934675, Mar 8, 1994

Filed:

Apr 3, 1991

Appl. No.:

7/679806

Inventors:

Gregory C. Buchner - South Daytona FL
Jeffrey D. Potter - Port Orange FL
Walter R. Steiner - Ormond Beach FL

International Classification:

G06F 1562

US Classification:

395122

Abstract:

A method for determining the proper occulation relationship between a calligraphic point and at least one of another calligraphic point and a surface in a raster image, divides the total image screen into an array of spans, each containing an ordered set of pixels which may be further divided into an array of subpixels; determines which of the subpixels on the total screen lie inside each of the raster surfaces and calligraphic points which must be considered for the image totality; then orders the distance of each of the raster surfaces from the viewing point and also orders the distance of each of the point features from the viewing point; and then compares the ordered distances of each point to at least one of the raster surface distances and other point distances to determine which of subpixels of the point or surface/other point are occluded and which subpixels are visible.

US Patent:

60725052, Jun 6, 2000

Filed:

Apr 1, 1998

Appl. No.:

9/053589

Inventors:

Thomas A. Piazza - Granite Bay CA
R. Scott Hartog - Orlando FL
Michael Mantor - Orlando FL
Jeffrey D. Potter - Winter Springs FL
Ralph Clayton Taylor - Deland FL
Michael A. Mang - Oviedo FL

Assignee:

Real 3D, Inc. - Orlando FL

International Classification:

G06T 100
G06F 1500

US Classification:

345501

Abstract:

A rasterizer comprised of a bounding box calculator, a plane converter, a windower, and incrementers. For each polygon to be processed, a bounding box calculation is performed which determines the display screen area, in spans, that totally encloses the polygon and passes the data to the plane converter. The plane converter also receives as input attribute values for each vertex of the polygon. The plane converter computes planar coefficients for each attribute of the polygon, for each of the edges of the polygon. The plane converter unit computes the start pixel center location at a start span and a starting coefficient value at that pixel center. The computed coefficients also include the rate of change or gradient, for each polygon attribute in the x and y directions, respectively. The plane converter also computes line coefficients for each of the edges of the polygon. Line equation values are passed through to the windower where further calculations allow the windower to determine which spans are either covered or intersected by the polygon.

US Patent:

50161938, May 14, 1991

Filed:

Apr 7, 1988

Appl. No.:

7/178934

Inventors:

Robert F. Stone - New Smyrna FL
Jeffrey D. Potter - Port Orange FL
William S. Beamon - Ormond Beach FL

Assignee:

General Electric Company - Syracuse NY

International Classification:

G06F 1568

US Classification:

364518

Abstract:

In computer image generation (CIG) systems, image data for defining pixel modulation values and for supporting a display having a predetermined resolution are determined for defining a scene. For some applications, such as for representing background and/or peripheral areas, it may be acceptable to use data having a lower resolution than the predetermined resolution. Method and apparatus for taking a portion of the image data obtain derived data by a predetermined combination of the portion of image data. Lines of composed data supplied to a display device include a sequence of pixel modulation values selected from the portion of image data and the derived data. In one embodiment the number of lines supported by the image data is doubled with each line containing 50% image data and 50% derived data. Pixel modulation values may be oversampled between adjacent lines of the display for obtaining derived data. Respective composed data for a plurality of display devices may be obtained from a respective plurality of portions of the image data, thus obviating the need to provide additional video processing channels along with associated hardware.