Jeffrey B Reed

US Patent:

D504284, Apr 26, 2005

Filed:

Nov 10, 2003

Appl. No.:

29/193534

Inventors:

Gary L. Corona - Dallas TX, US
Danny E. Swindler - Round Rock TX, US
Jeffrey A. Reed - Austin TX, US

Assignee:

DGC Enterprises, LLC - Dallas TX

International Classification:

0706

US Classification:

D 76004, D7707, D7708

US Patent:

7219326, May 15, 2007

Filed:

Dec 16, 2003

Appl. No.:

10/738278

Inventors:

Jeffrey B. Reed - Austin TX, US
James S. Blomgren - Austin TX, US
Donald W. Glowka - Austin TX, US
Timothy A. Olson - Austin TX, US
Thomas W. Rudwick - Austin TX, US

Assignee:

Intrinsity, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

716 18, 716 5

Abstract:

The matching algorithm of the layout synthesis method and apparatus disclosed locates transistor pattern matches in a design, links a parameterized tile to each identified match, and adjusts certain variable parameters of the linked parameterized tile to meet the physical design requirements of each located match. Each transistor pattern corresponds to a parameterized tile, which is an actual physical representation of the corresponding pattern and includes variable parameters, which may include transistor size. The matching algorithm locates matches in the design for an ordered list of patterns, names each located match, links the proper parameterized tile to each named match, and adjusts the tile's variable parameters as required. Transistors in the design are included in one and only one named located match.

US Patent:

8397190, Mar 12, 2013

Filed:

Aug 2, 2011

Appl. No.:

13/196005

Inventors:

Robert D. Kenney - Austin TX, US
Raymond C. Yeung - Round Rock TX, US
Paul K. Miller - Dripping Springs TX, US
Donald W. Glowka - Austin TX, US
Jeffrey B. Reed - Austin TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 17/50

US Classification:

716106, 716110, 716124, 716126, 716131, 716132, 716136, 716138, 716139, 703 13, 703 14

Abstract:

A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces. One of the new circuit blocks may be selected for physical build to obtain one or more physical instances corresponding to the selected new circuit block, and a top-level build may link each new circuit block instance to one of those one or more physical instances.

US Patent:

20090079201, Mar 26, 2009

Filed:

Sep 26, 2007

Appl. No.:

11/861575

Inventors:

Eduardo Escamilla - Round Rock TX, US
Maria C. Schlesener - Austin TX, US
Jeffrey A. Reed - Austin TX, US

International Classification:

H05K 7/00

US Classification:

292 10

Abstract:

A portable information handling system has an automatic latching system that maintains a lid having a display in a desired position relative to a housing, such as a closed position having the lid closed proximate the housing and including a tablet configuration having the display exposed in the closed position. A post automatically extends from the housing into the lid when in the closed position to prevent rotation of the lid. The post automatically retracts into the housing when the lid is in the open position to provide an aesthetically pleasing latch solution for tablet portable information handling systems.

US Patent:

20130111422, May 2, 2013

Filed:

Oct 31, 2011

Appl. No.:

13/285718

Inventors:

Jeffrey B. Reed - Austin TX, US
Brian J. Nalle - Austin TX, US
Michael A. Dukes - Wimberly TX, US

International Classification:

G06F 17/50

US Classification:

716102

Abstract:

Techniques and structures relating to consistency management for fabrication data are disclosed. A plurality of data sources may contain different values for a variety of design parameters usable by electronic circuit design tools to physically lay out at least a portion of an integrated circuit (such as minimum spacing rules, etc.). By seeking to detect different parameter values and/or parameter values that fail to meet a confidence threshold, potential errors may be uncovered at an earlier stage of the design process. Error detection may occur in response to a request to a database, or as part of a consistency check. Different file formats for different design tools may be imported into a central database to facilitate system operation, and an application programming interface may be used to acquire or calculate data values and perform checks in some embodiments.

US Patent:

48797588, Nov 7, 1989

Filed:

Jan 2, 1987

Appl. No.:

7/000276

Inventors:

Michael J. DeLuca - Boca Raton FL
Jeffrey B. Reed - Lake Worth FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 110

US Classification:

455296

Abstract:

A paging receiver and a method for minimizing spurious interference signals in the radio frequency (RF) stages and the intermediate frequency (IF) stages. The paging receiver includes a receiving means, a timing means, a voltage converting means, and a decoding means. A frequency for the timing signals generated by the timing means is selected to minimize spurious signal response. The timing signals are simultaneously applied to the decoding means and the voltage converting means. The frequency of the timing signal can be varied to minimize spurious signal response. The decoding means is notified of the timing signal frequency to effect the detecting and decoding of received coded information in real time.

US Patent:

48518298, Jul 25, 1989

Filed:

Dec 4, 1986

Appl. No.:

6/938093

Inventors:

Michael J. DeLuca - Boca Raton FL
Jeffrey B. Reed - Lake Worth FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04Q 700

US Classification:

34082544

Abstract:

The present invention relates to a paging receiver and a method for generating an alert indicating the status of memory. The paging receiver includes a plurality of memory storage areas, each memory storage storing a received message and including a corresponding value indicative of the status of the stored messages. The status values are priority ordered. The number of memory storage areas having status values not exceeding a first predetermined value is determined. If the number determined is below a second predetermined value, an alert is generated.

US Patent:

D4190912, Jan 18, 2000

Filed:

Apr 1, 1999

Appl. No.:

D/102809

Inventors:

Will Pattison - Austin TX
Jeffrey A. Reed - Cedar Park TX

Assignee:

Rochester Gauges, Inc. - Dallas TX

International Classification:

1004

US Classification:

D10101