Jeffrey Paul Rice

US Patent:

7635637, Dec 22, 2009

Filed:

Jul 25, 2005

Appl. No.:

11/189163

Inventors:

Qi Wang - West Jordan UT, US
Minhua Li - Sandy UT, US
Jeffrey H. Rice - South Jordan UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/30
H01L 21/46

US Classification:

438458, 438517, 257E21568

Abstract:

Processes used to transfer semiconductor structures from an initial substrate to a base substrate include bonding the initial substrate with a silicon dioxide layer to a doped silicon structure weakened sufficiently by hydrogen implantation for cleaving. After cleaving, a doped silicon layer remains, burying the silicon dioxide layer between the doped silicon layer and the initial substrate. Semiconductor structures are formed within/on an epitaxial layer disposed on the doped silicon layer forming an intermediate semiconductor structure. A process handle is temporarily bonded to the semiconductor structures for support. The initial substrate is thinned and removed by a mechanical thinning process followed by chemical etching using the buried silicon dioxide layer as an etch stop. The silicon dioxide layer is chemically removed from the doped silicon layer. A base substrate is formed on the doped silicon layer.

US Patent:

20080073350, Mar 27, 2008

Filed:

May 15, 2007

Appl. No.:

11/749140

Inventors:

Tim Clarot - Phoenix AZ, US
Samuel Belcher - Moscow OH, US
Louis Germanio - Vineland NJ, US
Jeffrey Rice - Dayton OH, US
Regina Miskewitz - Phoenix AZ, US

International Classification:

B65D 51/00
B65D 5/72

US Classification:

220361000, 222566000

Abstract:

Assemblies for storing and dispensing material, systems including an assembly and a composition, and methods of forming and using the assembly and systems are disclosed. An assembly may include a resilient vessel portion for storing material and a spout portion for directing the material as the material is dispensed from the system. The vessel portion and the spout portion may be formed separately and subsequently coupled together to form an assembly, or the vessel portion and the spout portion may be formed as a single unit.

US Patent:

20100035202, Feb 11, 2010

Filed:

May 15, 2007

Appl. No.:

12/300989

Inventors:

Tim Clarot - Phoenix AZ, US
Regina Miskewitz - Phoenix AZ, US
Samuel Belcher - Moscow OH, US
Louis Germanio, JR. - Vineland NJ, US
Jeffrey Rice - Dayton OH, US

Assignee:

ZICARE, LLC - Scottsdale AZ

International Classification:

A61C 19/06

US Classification:

433 80

Abstract:

Systems and kits dispensing material and methods of forming and using the systems and kits are disclosed. The system may include a deformable vessel portion for storing material and a spout portion for directing the material as the material is dispensed from the system. The vessel portion and the spout portion may be formed separately and subsequently coupled together to form the system.

US Patent:

20100052046, Mar 4, 2010

Filed:

Nov 9, 2009

Appl. No.:

12/614824

Inventors:

Qi Wang - West Jordan UT, US
Minhua Li - Sandy UT, US
Jeffrey H. Rice - South Jordan UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 29/78

US Classification:

257329, 257E29257, 257E29262

Abstract:

A semiconductor apparatus includes a metal substrate, a doped silicon layer on the metal substrate, a semiconductor layer overlying the doped silicon layer, and semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps. In an embodiment, the doped silicon layer comprises a heavily doped silicon layer. In another embodiment, the doped silicon region has a thickness that is less than a thickness of a cleavable region formed by ion implantation. In a specific embodiment, the thickness of the cleavable region is about 1-2 um. In another embodiment, the semiconductor layer has a thickness of approximately 10 um. In another embodiment, the semiconductor structures includes a vertical power MOSFET with the metal substrate configured to be a drain terminal contact region.

US Patent:

20230046399, Feb 16, 2023

Filed:

Oct 26, 2022

Appl. No.:

17/974318

Inventors:

- Orem UT, US
Michael Black - Orem UT, US
R. Stewart Nielson - Pleasant Grove UT, US
Bradley R. Williams - Pocatello ID, US
Benjamin Downard - Draper UT, US
Jeffrey H. Rice - South Jordan UT, US
JIm Pierce - Sandy UT, US

International Classification:

G02B 5/30

Abstract:

A reflective wire grid polarizer (WGP) can include an array of wires on a face of a substrate with channels between adjacent wires The wires can have certain characteristics for WGP performance, such as index of refraction, alternating high/low index continuous thin films, thickness of layer(s), duty cycle, reflective rib shape, a curved side of transparent ribs or aspect ratio, or combinations thereof.

US Patent:

20210018669, Jan 21, 2021

Filed:

Jul 2, 2020

Appl. No.:

16/919513

Inventors:

- Orem UT, US
Michael Black - Oram UT, US
R. Stewart Nielson - Pleasant Grove UT, US
Bradley R. Williams - Pocatello ID, US
Benjamin Downard - Draper UT, US
Jeffrey H. Rice - South Jordan UT, US
Jim Pierce - Sandy UT, US

International Classification:

G02B 5/30

Abstract:

A reflective wire grid polarizer (WGP) can include an array of wires on a face of a substrate , with channels between adjacent wires . The wires can have certain characteristics for WGP performance, such as index of refraction, alternating high/low index continuous thin films, thickness of layer(s), duty cycle, reflective rib shape, a curved side of transparent ribs or , aspect ratio, or combinations thereof.