Jeffrey Thomas Robertson

Address:

5434 Alteza Dr, Colorado Springs, CO 80917

VIN:

3D7JV1ETXBG605694

Make:

RAM

Model:

RAM PICKUP 1500

Year:

2011

Address:

8106 Silver Fox Cir, Glen Burnie, MD 21061

VIN:

5N1BV28U57N128370

Make:

NISSAN

Model:

QUEST

Year:

2007

US Patent:

6894535, May 17, 2005

Filed:

Dec 18, 2001

Appl. No.:

10/025353

Inventors:

Jeffrey Thomas Robertson - Wellington CO, US
Victoria Meier - Ft Collins CO, US
Paul D Nuber - Ft Collins CO, US

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

H03K019/173

US Classification:

326 46, 326 56

Abstract:

At least one column of a latch array includes a tri-state buffer in the upper portion of the column that receives the output of the uppermost group of latches of the column as its input, and which is enabled by a dump signal when a latch in the upper portion is addressed. When the dump signal that triggers the tri-state buffer is active, whatever is at the input of the tri-state buffer is driven by the buffer to the bottom of the latch array column, thereby providing the driven signal with sufficient strength to obviate transition timing and signal integrity problems. When the dump signal that triggers the tri-state buffer is not asserted, the tri-state buffer output exhibits high impedance, which isolates the lower portion of the latch array column from the upper portion of the latch array column, thereby preventing the capacitance associated with the line connecting the tri-state buffer to the output of the uppermost latch from affecting the driving ability of the latches in the lower portion of the column.

US Patent:

6948148, Sep 20, 2005

Filed:

Feb 5, 2002

Appl. No.:

10/068649

Inventors:

Victoria Meier - Ft Collins CO, US
William C Borough - Fort Collins CO, US
Jeffrey Thomas Robertson - Wellington CO, US

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G06F017/50

US Classification:

716 18, 716 11, 716 14

Abstract:

Generating a data path macro cell based upon a text format template comprising variables. The system provides for creating a text format template by generating a text format representation of a data path macro cell based upon data representing a graphical layout of the data path macro cell. Variables are substituted for constants. Variables are changed to values associated with a macro cell having desired characteristics to create a text format file representative of a desired macro cell. Graphical data representing the layout of a macro cell is generated based upon the text format file.

US Patent:

6978406, Dec 20, 2005

Filed:

May 24, 2002

Appl. No.:

10/155544

Inventors:

Gayvin E Stong - Fort Collins CO, US
Jeffrey Thomas Robertson - Wellington CO, US

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G11C029/00

US Classification:

714718

Abstract:

A memory array test system and method provides for testing a memory array in a manufactured chip. In accordance with one aspect of the invention, a system includes memory test input logic that acquires test data via a data port, a memory test enable logic and a memory test output logic. In accordance with another aspect of the invention, a method acquires test data via a data port, writes the test data to a memory address in the memory array, and reads output data from the memory address in the memory array. Then, the method compares the test data and the output data to determine if the memory address in the memory array passes a test.

US Patent:

7257751, Aug 14, 2007

Filed:

Oct 30, 2001

Appl. No.:

10/021374

Inventors:

Gayvin E Stong - Fort Collins CO, US
Jeffrey Thomas Robertson - Wellington CO, US
David James Mielke - Fort Collins CO, US

International Classification:

G01R 31/28

US Classification:

714733

Abstract:

An apparatus permits built-in self-test (“BIST”) of an IC that includes a memory element having more than one impermissible operation. A code generator accepts a clock signal and generates a test code in response to it. A decoder accepts the test code and generates at least two output lines to disable the impermissible operations during the test. When the decoder is in a decode disabled condition, the output lines reflect a value that permit all possible memory operations.