Jeffrey Allen Sabrowski

US Patent:

20140068322, Mar 6, 2014

Filed:

Aug 29, 2012

Appl. No.:

13/598072

Inventors:

Edgar R. Cordero - Round Rock TX, US
Joab D. Henderson - Pflugerville TX, US
Divya Kumar - Austin TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 11/14

US Classification:

714 611, 714E11113

Abstract:

A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.

US Patent:

20130179724, Jul 11, 2013

Filed:

Jan 5, 2012

Appl. No.:

13/343938

Inventors:

Edgar R. Cordero - Round Rock TX, US
Joab D. Henderson - Austin TX, US
Divya Kumar - Austin TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 11/20

US Classification:

714 63, 714E11089

Abstract:

A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.

US Patent:

20180067874, Mar 8, 2018

Filed:

Nov 8, 2017

Appl. No.:

15/807187

Inventors:

- Armonk NY, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Saravanan Sethuraman - Bangalore, IN
Kenneth L. Wright - Austin TX, US

International Classification:

G06F 12/14
G06F 21/79

Abstract:

This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.

US Patent:

20160027494, Jan 28, 2016

Filed:

Oct 8, 2015

Appl. No.:

14/878174

Inventors:

- Armonk NY, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US

International Classification:

G11C 11/406
G11C 11/4076

Abstract:

A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.

US Patent:

20150278005, Oct 1, 2015

Filed:

Jun 23, 2014

Appl. No.:

14/312327

Inventors:

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

International Classification:

G06F 11/07

Abstract:

A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

US Patent:

20150278086, Oct 1, 2015

Filed:

Mar 27, 2014

Appl. No.:

14/227187

Inventors:

- Armonk NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/02
G06F 11/10

Abstract:

A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

US Patent:

20150228328, Aug 13, 2015

Filed:

Apr 23, 2015

Appl. No.:

14/694067

Inventors:

- Armonk NY, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US

International Classification:

G11C 11/4099
G11C 11/4076
G11C 11/4091
G11C 11/406

Abstract:

A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.

US Patent:

20150213853, Jul 30, 2015

Filed:

Jan 30, 2014

Appl. No.:

14/168102

Inventors:

- ARMONK NY, US
Carlos A. Fernandez - Hialeah FL, US
Joab D. Henderson - Pflugerville TX, US
Jeffrey A. Sabrowski - Leander TX, US
Anuwat Saetow - Austin TX, US
Saravanan Sethuraman - Bangalore, IN

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G11C 7/10

Abstract:

A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.