Jeffrey Allan Shields

US Patent:

6350696, Feb 26, 2002

Filed:

Sep 28, 2000

Appl. No.:

09/671209

Inventors:

Jeffrey A. Shields - Sunnyvale CA
Jeffrey P. Erhardt - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438704, 438696, 438305, 438592, 438595, 438655, 438682, 438734, 438750

Abstract:

Spacers are formed on a semiconductor device by depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a portion of the spacer layer covering the semiconductor device. The semiconductor device is then subjected to an isotropic etching process to form the spacers on the semiconductor device.

US Patent:

6376877, Apr 23, 2002

Filed:

Feb 24, 2000

Appl. No.:

09/513260

Inventors:

Allen S. Yu - Fremont CA
Jeffrey A. Shields - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257317, 257315, 257321, 257510

Abstract:

A reduced device geometry and increased device efficiency semiconductor memory device is provided. The method of manufacturing the semiconductor memory device includes forming shallow trench isolations (STIs) on the semiconductor substrate, forming a photoresist mask over the STIs, selectively etching the STIs to form curved surface area profiles, growing a layer of tunnel oxide (TOX) over exposed areas of the semiconductor substrate, forming a first polysilicon (poly) layer over the TOX layer and the STIs, chemical-mechanical polishing (CMP) the first poly layer, forming an oxide-nitride-oxide (ONO) layer over the first poly layer, and forming a second poly layer over the ONO layer.

US Patent:

6383945, May 7, 2002

Filed:

Oct 29, 1999

Appl. No.:

09/430465

Inventors:

Jiahua Huang - San Jose CA
Jeffrey A. Shields - Sunnyvale CA
Allison Holbrook - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21203

US Classification:

438734, 438713, 438714, 438723, 438724, 438701, 438725, 438739, 438740, 430 5

Abstract:

An improved etch of thick protective topside stack films, which cover metal pads of a semiconductor device. The invention uses a downstream plasma isotropic etch to etch the topside stack film. In one embodiment, the downstream plasma isotropic etch is used to etch only part of the topside stack films. A subsequent anisotropic oxide plasma etch is used to etch the remaining topside stack film to the metal pads. In another embodiment, the downstream plasma isotropic etch is used to etch completely through the topside stack films to the metal pad. The invention allows the etching through topside stack films greater than 5 microns.

US Patent:

6412498, Jul 2, 2002

Filed:

Mar 24, 2000

Appl. No.:

09/533999

Inventors:

Jeffrey A. Shields - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

134 12, 134 13, 438715, 438725, 216 49, 216 67

Abstract:

A method for plasma stripping a defective resist from a wafer that significantly reduces formation of residue between metal lines caused by conventional plasma stripping methodology and eliminates bridging, short-circuiting, and device failure caused thereby. The method includes locating a wafer in a chamber having a platen, reducing a pressure in the chamber to a predetermined pressure, and placing the wafer in contact with the platen to heat the wafer. In the method, the wafer is heated to a temperature below approximately 210Â C. and is then moved away from the platen while the wafer temperature is below approximately 210Â C. Plasma stripping a resist layer is then performed while maintaining the wafer temperature below approximately 210Â C. By maintaining the temperature of the wafer below approximately 210Â C. , residue formation is substantially prevented and product yield is improved.

US Patent:

6426301, Jul 30, 2002

Filed:

Jul 31, 2000

Appl. No.:

09/628822

Inventors:

Jeffrey A. Shields - Sunnyvale CA
Ramkumar Subramanian - San Jose CA
Bharath Rangarajan - Santa Clara CA
Allen S. Yu - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438706, 438720

Abstract:

A wafer having a substrate and an insulating layer over the substrate that includes a conductive layer over the insulating layer. The conductive layer mitigates charges formed on a photoresist layer during etching of features (e. g. , vias and trenches). Any conductive material may serve this purpose. For example, aluminum, tantalum nitride, titanium and titanium nitride. Typically, a plasma etcher is employed for forming vias and trenches in an insulating layer to create contacts and conducting lines used to connect devices residing within different layers. The plasma etcher causes charge buildup on a photoresist layer that is utilized during the etching process. The charge buildup causes potential differences on the photoresist layer, which can lead to eventual damage of devices. A conductive layer eliminates this potential differences because a charge equilibrium is established due to the conductivity of the conductive layer.

US Patent:

6440874, Aug 27, 2002

Filed:

Mar 24, 2000

Appl. No.:

09/534000

Inventors:

Jeffrey A. Shields - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2131

US Classification:

438758, 438725, 438743, 438723, 438963

Abstract:

The invention relates to the field of manufacturing semiconductor devices, particularly processes directed to resist removal. In the method of the invention, the wafer temperature is maintained below approximately 210Â C. to 220Â C. to prevent residue formation, by controlling the temperature of a platen or paddle adjancent a wafer to be less than about 210Â C. throughout plasma stripping of a resist layer disposed on the wafer. Moreover, to achieve a suitable yield and throughput at these temperatures, the flow rate of an additive to gases supplied to a plasma chamber to create an O plasma is controlled to thereby control and improve a resist striprate at these temperatures.

US Patent:

6441418, Aug 27, 2002

Filed:

Nov 1, 1999

Appl. No.:

09/430848

Inventors:

Jeffrey A. Shields - Sunnyvale CA
Bharath Rangarajan - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 31062

US Classification:

257296, 257775

Abstract:

A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, forming spacers along the side walls of the first aperture, creating a second aperture in the first insulating layer below the first aperture, and filling the aperture with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.

US Patent:

6472751, Oct 29, 2002

Filed:

Sep 6, 2000

Appl. No.:

09/656437

Inventors:

Robert C. Chen - Los Altos CA
Jeffrey A. Shields - Sunnyvale CA
Robert Dawson - Austin TX
Khanh Tran - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2940

US Classification:

257758, 257759, 257760, 257774, 257700, 257787, 257649, 257751, 438687, 438688, 438689

Abstract:

A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-containing dielectric layer is formed over the dielectric interlayer having the nitrided barrier layer thereon. The nitrided barrier layer serves as a barrier to diffusion of hydrogen from the at least one hydrogen-containing dielectric layer into the dielectric interlayer, thereby preventing a decrease in hot carrier injection reliability.