Jeffrey Lawrence Summers

US Patent:

6829731, Dec 7, 2004

Filed:

Aug 14, 2000

Appl. No.:

09/638757

Inventors:

Peter Dean LaFauci - Holly Springs NC
Rhonda Gurganious Mitchell - Fuquay-Varina NC
Jeffrey Richard Summers - Raleigh NC

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05F 1100

US Classification:

714 33, 714 43, 714 38

Abstract:

A method and system for automating the creation of test cases for logic designs. A comprehensive set of bus transactions characterizing a bus architecture is provided to a test case designer in a user interface. The designer may enter inputs corresponding to a particular design-under-test (DUT) via the interface. The interface processes the inputs to automatically generate a configuration file corresponding to the particular DUT. The configuration file may be processed by a generator program to automatically generate a test case comprising one or more bus transactions customized to the particular DUT.

US Patent:

7467366, Dec 16, 2008

Filed:

Sep 26, 2006

Appl. No.:

11/535203

Inventors:

John B. Blankenship - Raleigh NC, US
Kevin N. Magill - Raleigh NC, US
Jeffrey R. Summers - Raleigh NC, US
Anup Wadia - Wake Forest NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45
G06F 17/50

US Classification:

716 6, 716 4, 716 5, 703 19

Abstract:

A method for generating a timing path software monitor for identifying a critical timing path in hardware devices coupled between first and second components is provided. The method includes generating a static timing report associated with the hardware devices. The static timing report has names of the hardware devices and wire names associated with wires coupled to the hardware devices. The method further includes automatically generating the timing path software monitor based on the static timing report that monitors binary values associated with the wire names at a first clock cycle and a transition of binary values associated with the wire names during a second clock cycle after the first clock cycle. The timing path software monitor indicates a critical timing path is identified when the transition of one of the binary values received by the second component occurs during the second clock cycle.

US Patent:

7610449, Oct 27, 2009

Filed:

Oct 4, 2006

Appl. No.:

11/538458

Inventors:

Gordon T. Davis - Chapel Hill NC, US
Richard W. Doing - Raleigh NC, US
John D. Jabusch - Cary NC, US
M V V Anil Krishna - Cary NC, US
Brett Olsson - Cry NC, US
Eric F. Robinson - Raleigh NC, US
Sumedh W. Sathaye - Cary NC, US
Jeffrey R. Summers - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711122, 711125, 712237

Abstract:

A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.

US Patent:

7716264, May 11, 2010

Filed:

Aug 16, 2005

Appl. No.:

11/205987

Inventors:

Sherman M. Dance - Rochester MN, US
Jeffrey R. Summers - Raleigh NC, US
Shivakumar Swaminathan - Morrisville NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/00

US Classification:

708209, 708505

Abstract:

An apparatus for performing alignment shifting in a floating-point unit is disclosed. An alignment shifter includes a shift amount calculator, a set of first level shifters and a set of second level shifter. The shift amount calculator generates one shift amount under a double-precision mode and two shift amounts under a single-precision mode. The first level shifters can concurrently receive two double-precision mantissas under the double-precision mode or two single-precision mantissas under the single-precision mode. The first level of shifts performs small shifts concurrently on the two double-precision mantissas according to the single shift amount, or on the two single-precision mantissas according to the two shift amounts. The second level shifters performs large shifts on outputs from the first level shifters to generate one double-precision floating-point result or two single-precision floating-point results.

US Patent:

7760669, Jul 20, 2010

Filed:

Jun 27, 2006

Appl. No.:

11/426746

Inventors:

Timothy Hume Heil - Rochester MN, US
Michael Steven Siegel - Raleigh NC, US
Jeffrey R. Summers - Raleigh NC, US
Steven Paul VanderWiel - Rosemount MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/43

US Classification:

370258, 370403, 370460

Abstract:

In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.

US Patent:

7779232, Aug 17, 2010

Filed:

Aug 28, 2007

Appl. No.:

11/845838

Inventors:

Richard W. Doing - Raleigh NC, US
Michael O. Klett - Raleigh NC, US
Kevin N. Magill - Raleigh NC, US
Brian R. Mestan - Austin TX, US
David Mui - Round Rock TX, US
Balaram Sinharoy - Poughkeepsie NY, US
Jeffrey R. Summers - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/42
G06F 9/312

US Classification:

712207

Abstract:

A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.

US Patent:

7826399, Nov 2, 2010

Filed:

Mar 5, 2008

Appl. No.:

12/042612

Inventors:

Timothy Hume Heil - Rochester MN, US
Michael Steven Siegel - Raleigh NC, US
Jeffrey R. Summers - Raleigh NC, US
Steven Paul VanderWiel - Rosemount MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/43

US Classification:

370258, 370403, 370460

Abstract:

A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.

US Patent:

7934081, Apr 26, 2011

Filed:

Oct 5, 2006

Appl. No.:

11/538831

Inventors:

Gordon T. Davis - Chapel Hill NC, US
Richard W. Doing - Raleigh NC, US
John D. Jabusch - Cary NC, US
M V V Anil Krishna - Cary NC, US
Brett Olsson - Cry NC, US
Eric F. Robinson - Raleigh NC, US
Sumedh W. Sathaye - Cary NC, US
Jeffrey R. Summers - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/40
G06F 12/08

US Classification:

712239, 711122, 711125

Abstract:

A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.