Jeffrey E Trull

US Patent:

6405305, Jun 11, 2002

Filed:

Sep 10, 1999

Appl. No.:

09/394024

Inventors:

Stephan G. Meier - Mountain View CA
Jeffrey E. Trull - San Jose CA
Derrick R. Meyer - Austin TX
Norbert Juffa - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9302

US Classification:

712222, 712226, 712221, 712224, 712245, 712217, 712227, 708510

Abstract:

A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating point unit is configured to schedule instructions older than the FLDCW-type instruction before the FLDCW-type instruction is scheduled. The FLDCW-type instruction acts as a barrier to prevent instructions occurring after the FLDCW-type instruction in program order from executing before the FLDCW-type instruction. Indicator bits may be used to simplify instruction scheduling, and copies of the floating point control word may be stored for instruction that have long execution cycles. A method and computer configured to rapidly execute FLDCW-type instructions in an out of program order context are also disclosed.

US Patent:

6460130, Oct 1, 2002

Filed:

Mar 30, 1999

Appl. No.:

09/281079

Inventors:

Jeffrey E. Trull - San Jose CA
Eric W. Mahurin - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

712 32, 711154, 710 57

Abstract:

A microprocessor having an instruction queue capable of out-of-order instruction dispatch and efficiently detect full conditions is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations and may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. The microprocessor may be further configured with high speed control logic coupled to the instruction queue. Instead of determining exactly how many empty storage locations are present in the queue, the control logic may be configured to determine whether the number of non-overlapping strings of empty storage locations is greater than or equal to the number of estimated instructions currently on their way to being stored in the instruction queue. A data queue and method for managing a queue are also disclosed, as is a computer system utilizing the above-mentioned microprocessor.

US Patent:

6487653, Nov 26, 2002

Filed:

Aug 25, 1999

Appl. No.:

09/383138

Inventors:

Stuart F. Oberman - Sunnyvale CA
Stephan G. Meier - Sunnyvale CA
Jeffrey E. Trull - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 738

US Classification:

712222, 708508

Abstract:

A microprocessor configured to dynamically switch its floating point load pipeline length from one stage in length to more than one stage in length is disclosed. The microprocessor may perform normal loads and detect denormal loads in a single clock cycle. The microprocessor temporarily stores each scheduled floating point instruction in a reissue buffer for at least one clock cycle. When a denormal load instruction is detected, the microprocessor is configured to add one or more stages to the floating point load pipeline to allow the denormal value to complete the conversion to an internal format. The longer pipeline is then used for all loads that follow the denormal load until there is an idle clock cycle or an abort occurs. At that point, the pipeline reverts back to its original shorter state. In addition, the microprocessor may be configured to cancel instructions scheduled assuming the denormal load would take only one clock cycle to complete.

US Patent:

7188325, Mar 6, 2007

Filed:

Oct 4, 2004

Appl. No.:

10/957848

Inventors:

Marius Evers - Sunnyvale CA, US
Jeffrey E. Trull - San Jose CA, US
Alper Halbutogullari - Santa Clara CA, US
Robert W. Williams - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 2

Abstract:

In one embodiment, a method for selecting transistor threshold voltages on an integrated circuit may include assigning a first threshold voltage to selected groups of transistors such as cell instances, for example, and determining which of the selected groups of transistors to assign a second threshold voltage, that is lower than the first threshold voltage, by iteratively performing a cost/benefit analysis. The method may further include determining which of the selected groups of transistors having a third threshold voltage to assign the first threshold voltage by iteratively performing a cost/benefit analysis. The cost/benefit analysis may include calculating a cost/benefit ratio for each group of the selected groups of transistors. In addition, the cost/benefit analysis may include calculating an upcone benefit and a downcone benefit for groups of transistors coupled to one or more inputs and outputs, respectively.

US Patent:

6185672, Feb 6, 2001

Filed:

Feb 19, 1999

Appl. No.:

9/253466

Inventors:

Jeffrey E. Trull - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

712217

Abstract:

A microprocessor having an instruction queue capable of out-of-order instruction dispatch and compaction of unaligned strings of empty storage locations is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations, each coupled to a single destination storage location. The instruction queue may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. As the instructions are output, gaps of empty storage locations may be formed in the queue. The microprocessor may be configured to compact out strings of empty storage locations greater than a predetermined number. This compaction may be performed by selectively shifting the instructions remaining in the queue either zero or N storage locations, wherein N is a predetermined positive integer.

US Patent:

57548129, May 19, 1998

Filed:

Jan 26, 1996

Appl. No.:

8/592209

Inventors:

John G. Favor - San Jose CA
Amos Ben-Meir - Cupertino CA
Warren G. Stapleton - San Jose CA
Jeffrey E. Trull - San Jose CA
Mark E. Roberts - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9312

US Classification:

395392

Abstract:

Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in accordance with the present invention to hold younger stores until the completion of older loads (and to hold younger loads until completion of older stores). Address matching logic allows a load-store execution controller constructed in accordance with the present invention to avoid load-store (and store-load) dependencies. Propagate-kill scan chains supply the relative age indications of loads with respect to stores (and of stores with respect to loads).

US Patent:

62471147, Jun 12, 2001

Filed:

Feb 19, 1999

Appl. No.:

9/253478

Inventors:

Jeffrey E. Trull - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 930

US Classification:

712216

Abstract:

A microprocessor having an instruction queue capable of out-of-order instruction dispatch and rapidly selecting one or more oldest eligible entries is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations and may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. The microprocessor may be further configured with high speed control logic coupled to the instruction queue. The control logic may comprise a number of pluralities of multiplexers, wherein the first plurality of multiplexers are configured to select a first subset of the instructions stored in the queue. The second plurality of multiplexers then select a second subset of instructions from the first subset. This process is repeated in each successive plurality of multiplexers until the oldest eligible entry is selected.

US Patent:

60386576, Mar 14, 2000

Filed:

Mar 17, 1998

Appl. No.:

9/040087

Inventors:

John G. Favor - San Jose CA
Amos Ben-Meir - Cupertino CA
Warren G. Stapleton - San Jose CA
Jeffrey E. Trull - San Jose CA
Mark E. Roberts - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9312

US Classification:

712216

Abstract:

Scan logic which tracks the relative age of stores with respect to a particular load (or of loads with respect to a particular store) allows at processor to hold younger stores until the completion of older loads (or to hold younger loads until completion of older stores). Embodiments of propagate-kill style lookahead scan logic or of tree-structured, hierarchically-organized scan logic constructed in accordance with the present invention provide store older and load older indications with very few gate delays, even in processor embodiments adapted to concurrently evaluate large numbers of operations. Operating in conjunction with the scan logic, address matching logic allows the processor to more precisely tailor its avoidance of load-store (or store-load) dependencies. In a processor having a load unit and a store unit, a load/store execution control system allows load and store instructions to execute generally out-of-order with respect to each other while enforcing data dependencies between the load and store instructions.