Jeffrey Allen West

US Patent:

6358849, Mar 19, 2002

Filed:

Dec 21, 1999

Appl. No.:

09/467680

Inventors:

Robert H. Havemann - Garland TX
Girish A. Dixit - San Jose CA
Manoj Jain - Plano TX
Eden Zielinski - Boise ID
Jeffrey West - San Antonio TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21302

US Classification:

438689, 438700, 438723, 438724

Abstract:

A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.

US Patent:

7309651, Dec 18, 2007

Filed:

Oct 30, 2003

Appl. No.:

10/697137

Inventors:

Jeffrey A. West - Dallas TX, US
Michael D. Barth - Plano TX, US
Steven P. Zuhoski - Rowlett TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44

US Classification:

438687, 438658

Abstract:

Doping copper interconnects () with silicon () has been shown to improve Electromigration and Via Stress Migration reliability. After copper () is deposited by electrochemical deposition and chemically-mechanically polished back, doping is achieved by flowing SiHover the copper interconnect () for 0. 5 to 5 seconds at a temperature of 325-425 C.

US Patent:

7943514, May 17, 2011

Filed:

Sep 3, 2009

Appl. No.:

12/553879

Inventors:

Jeffrey A West - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44

US Classification:

438667, 438622, 438666, 257E21597

Abstract:

An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer.

US Patent:

8039385, Oct 18, 2011

Filed:

Sep 13, 2010

Appl. No.:

12/880629

Inventors:

Jeffrey A. West - Dallas TX, US
Young-Joon Park - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/44
H01L 21/4763

US Classification:

438613, 438637, 438639, 438652, 257E23033, 257E23067, 257E23069

Abstract:

A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve and an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to the protruding TSV tips is on a portion of the sidewalls of the protruding TSV tips. The passivation layers is absent from a distal portion of the protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends including a first metal layer including a first metal other than solder and a second metal layer including a second metal other than solder that covers the exposed tip portion. The bulbous distal tip ends cover a portion of the TSV sidewalls and are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ≧25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

US Patent:

8097964, Jan 17, 2012

Filed:

Dec 29, 2009

Appl. No.:

12/648871

Inventors:

Jeffrey Alan West - Dallas TX, US
Masazumi Amagai - Tsukuba, JP

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257786, 257698

Abstract:

An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.

US Patent:

8125053, Feb 28, 2012

Filed:

Feb 4, 2009

Appl. No.:

12/365333

Inventors:

Jeffrey A. West - Dallas TX, US
Patricia Diane Vincent - Prosper TX, US
Robert A. Tuerck - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/544

US Classification:

257620, 257621, 257623, 257E23194

Abstract:

A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape, with the die separated by a plurality of scribe lanes. An existing die seal generally protects the boundary of the die but can still fail to fully protect the die from excessive cracks induced by dicing damage, particularly when dicing through brittle, low-k dielectrics. The system, method, and apparatus includes embedding a crack arrest structure (CAS) between adjacent scribe lanes. Upon a mechanical saw dicing the wafer, the CAS creates a moisture diffusion block, and can absorb or significantly diminish the energy of cracks propagating towards the individual die seals. Furthermore, the system, method, and apparatus can be implemented without the need to increase the width of the scribe lanes.

US Patent:

8125054, Feb 28, 2012

Filed:

Sep 23, 2009

Appl. No.:

12/565748

Inventors:

Jeffrey Alan West - Dallas TX, US
Craig Beddingfield - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/544
H01L 21/00

US Classification:

257620, 257E22011, 257E21214, 438106

Abstract:

In a semiconductor device for use in a wafer level chip scale package (WLCSP) and a method for fabrication, an inner scribe seal is formed around a functional circuit area that does not extend all the way into the corners of the rectangular die, and an outer scribe seal follows the perimeter of the die and into the corners, with the outer scribe seal having a continuous barrier wall towards the die edges so that moisture penetration in dielectric layers of the die is minimized, and cracks and delamination are stopped near the die edges. Limiting the extent of the insulating layer or layers in the WLCSP to cover the functional circuit area also reduces the stresses caused by these layers near the die corners.

US Patent:

8143704, Mar 27, 2012

Filed:

Oct 2, 2009

Appl. No.:

12/572615

Inventors:

Jeffrey A West - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/40

US Classification:

257621, 257774, 257777, 257E23011, 257E23023, 257E23145, 257E21519, 257E21597

Abstract:

An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one protruding bonding feature having sidewall surfaces and a leading edge surface extending outward from the IC die. A workpiece has a workpiece surface including at least one electrical connector and at least one framed hollow receptacle coupled to the electrical connector. The receptacle is formed from metal and includes sidewall portions and a bent top that defines a cavity. The bent top includes bent peripheral shelf regions that point downward into the cavity and towards the sidewall portions. The protruding bonding feature is inserted within the cavity of the receptacle and contacts the bent peripheral shelf regions along a contact area to form a metallic joint, wherein the contact area is at least primarily along the sidewall surfaces.