Jeffrey M Wilkinson

US Patent:

20130235663, Sep 12, 2013

Filed:

Oct 31, 2012

Appl. No.:

13/665409

Inventors:

Paul B. Patterson - Gilbert AZ, US
Glen W. Benton - Chandler AZ, US
Jeffrey D. Wilkinson - Vadnais Heights MN, US

Assignee:

MEDTRONIC, INC. - Minneapolis MN

International Classification:

G11C 16/30

US Classification:

36518503, 36518521

Abstract:

Electrically erasable flash memory and method. The memory has a data storage element and a voltage sensing circuit. The data storage element is configured to store data bits, each of the data bits having a data state. The voltage sensing circuit is selectively coupled to individual ones of data bits and is configured to bias the data bits with at least one of a bias current and a bias resistance and to read the data state of the individual ones of the plurality of data bits.

US Patent:

20130235672, Sep 12, 2013

Filed:

Oct 31, 2012

Appl. No.:

13/665461

Inventors:

Paul B. Patterson - Gilbert AZ, US
Glen W. Benton - Chandler AZ, US
Jeffrey D. Wilkinson - Vadnais Heights MN, US

Assignee:

Medtronic, Inc. - Minneapolis MN

International Classification:

G11C 16/04

US Classification:

36518518

Abstract:

Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.

US Patent:

62863460, Sep 11, 2001

Filed:

Apr 30, 1998

Appl. No.:

9/070407

Inventors:

Robert W. Hocken - Scottsdale AZ
Kevin K. Walsh - Glendale AZ
Jeffrey D. Wilkinson - Vadnais Heights MN

Assignee:

Medtronic, Inc. - Minneapolis MN

International Classification:

G06F 9302

US Classification:

70260

Abstract:

A method and apparatus including conditional add and conditional add/subtract instructions are provided for use in the instruction set of a medical device instruction processor. More specifically, the conditional add and add/subtract instructions are provided to add two operands if a predetermined condition is satisfied within the instruction processor hardware. Additionally, the conditional add/subtract instruction may be used to subtract one operand from another operand if the predetermined condition is not satisfied. These instructions are adapted for use in implementing an efficient, interruptible, firmware-controlled multiplication or division mechanism. The inventive system allows multiplication or division operations to be interrupted at various intermediate points during the multiplication or division operation to thereby reducing interrupt latency.