Jeong Ja Kim

US Patent:

20220359697, Nov 10, 2022

Filed:

Jul 21, 2022

Appl. No.:

17/870401

Inventors:

- Santa Clara CA, US
Rahul RAMASWAMY - Portland OR, US
Jeong Dong KIM - Scappoose OR, US
Babak FALLAHAZAD - Portland OR, US
Ting CHANG - Portland OR, US
Nidhi NIDHI - Hillsboro OR, US
Walid M. HAFEZ - Portland OR, US

International Classification:

H01L 29/423
H01L 29/06
H01L 29/66
H01L 21/02
H01L 29/10
H01L 29/165

Abstract:

Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

US Patent:

20210280683, Sep 9, 2021

Filed:

Mar 5, 2020

Appl. No.:

16/810156

Inventors:

- Santa Clara CA, US
Rahul RAMASWAMY - Portland OR, US
Jeong Dong KIM - Scappoose OR, US
Babak FALLAHAZAD - Portland OR, US
Ting CHANG - Portland OR, US
Nidhi NIDHI - Hillsboro OR, US
Walid M. HAFEZ - Portland OR, US

International Classification:

H01L 29/423
H01L 29/06
H01L 29/66
H01L 29/165
H01L 29/10
H01L 21/02

Abstract:

Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

US Patent:

20210257452, Aug 19, 2021

Filed:

Feb 19, 2020

Appl. No.:

16/795081

Inventors:

- Santa Clara CA, US
Jeong Dong KIM - Scappoose OR, US
Walid M. HAFEZ - Portland OR, US
Rahul RAMASWAMY - Portland OR, US
Ting CHANG - Portland OR, US
Babak FALLAHAZAD - Portland OR, US

International Classification:

H01L 29/06
H01L 29/10
H01L 27/088
H01L 29/423
H01L 29/08
H01L 21/8234

Abstract:

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

US Patent:

20210257453, Aug 19, 2021

Filed:

May 5, 2021

Appl. No.:

17/308900

Inventors:

- Santa Clara CA, US
Jeong Dong KIM - Scappoose OR, US
Walid M. HAFEZ - Portland OR, US
Rahul RAMASWAMY - Portland OR, US
Ting CHANG - Portland OR, US
Babak FALLAHAZAD - Portland OR, US

International Classification:

H01L 29/06
H01L 29/423
H01L 29/10
H01L 29/08
H01L 27/088

Abstract:

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

US Patent:

20180090336, Mar 29, 2018

Filed:

Sep 22, 2017

Appl. No.:

15/712498

Inventors:

- Urbana IL, US
Jeong Dong Kim - Hillsboro OR, US

International Classification:

H01L 21/306
H01L 21/768
H01L 21/02
C23F 1/44
C23F 1/12

Abstract:

A method of catalyst-assisted chemical etching with a vapor-phase etchant has been developed. In one approach, a semiconductor substrate including a patterned titanium nitride layer thereon is heated, and an oxidant and an acid are evaporated to form a vapor-phase etchant comprising an oxidant vapor and an acid vapor. The semiconductor substrate and the patterned titanium nitride layer are exposed to the vapor-phase etchant during the heating of the semiconductor substrate. The vapor-phase etchant diffuses through the patterned titanium nitride layer, and titanium nitride-covered regions of the semiconductor substrate are etched. Thus, an etched semiconductor structure is formed.