Jeong R Kim

US Patent:

7154749, Dec 26, 2006

Filed:

Jun 8, 2004

Appl. No.:

10/863103

Inventors:

Zoran Stefanoski - Menlo Park CA, US
Jeong H. Kim - Hayward CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H05K 7/20
F28D 15/00

US Classification:

361695, 165 803, 16510433, 361700

Abstract:

One embodiment of a system for efficiently cooling a processor includes a mounting plate configured to be thermally coupled to the processor, a passive heat transport device thermally coupled to the mounting plate and a heat exchanger coupled to the passive heat transport device.

US Patent:

7359197, Apr 15, 2008

Filed:

Apr 12, 2004

Appl. No.:

10/822958

Inventors:

Zoran Stefanoski - Menlo Park CA, US
Jeong H. Kim - Hayward CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H05K 7/20

US Classification:

361699, 361689, 361695, 361697, 174 151, 174 161, 174 163, 165 803, 165 804, 16510433

Abstract:

One embodiment of a system for efficiently cooling a processor includes an active hybrid heat transport module adapted to be integrated with a fansink. The hybrid heat transport module comprises both a fluid channel and an air channel adapted for transporting heat. The hybrid heat transport module and the fansink may be used alone or in combination to dissipate heat from the processor.

US Patent:

7542292, Jun 2, 2009

Filed:

Apr 14, 2008

Appl. No.:

12/102828

Inventors:

Zoran Stefanoski - Menlo Park CA, US
Jeong H. Kim - Hayward CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H05K 7/20

US Classification:

361699, 361689, 361695, 361697, 174 151, 174 161, 174 163, 165 803, 165 804, 16510433

Abstract:

One embodiment of a system for efficiently cooling a processor includes an active hybrid heat transport module adapted to be integrated with a fansink. The hybrid heat transport module comprises both a fluid channel and an air channel adapted for transporting heat. The hybrid heat transport module and the fansink may be used alone or in combination to dissipate heat from the processor.

US Patent:

7969733, Jun 28, 2011

Filed:

Dec 17, 2008

Appl. No.:

12/336851

Inventors:

Samuel Abbay - San Francisco CA, US
Jeong Hun Kim - Sunnyvale CA, US
Don Le - Santa Clara CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H05K 7/20

US Classification:

361695, 361699, 361719, 361721, 174 151, 174 161, 165 803, 165 804, 16510433

Abstract:

A heat transfer system, method, and computer program product are provided for use with multiple circuit board environments. In use, a heat transfer component configured to be situated between a first circuit board and a second circuit board is provided. Such heat transfer component is in thermal communication with a first processor of the first circuit board and a second processor of the second circuit board. Furthermore, the heat transfer component is situated between the first circuit board and the second circuit board.

US Patent:

20220359697, Nov 10, 2022

Filed:

Jul 21, 2022

Appl. No.:

17/870401

Inventors:

- Santa Clara CA, US
Rahul RAMASWAMY - Portland OR, US
Jeong Dong KIM - Scappoose OR, US
Babak FALLAHAZAD - Portland OR, US
Ting CHANG - Portland OR, US
Nidhi NIDHI - Hillsboro OR, US
Walid M. HAFEZ - Portland OR, US

International Classification:

H01L 29/423
H01L 29/06
H01L 29/66
H01L 21/02
H01L 29/10
H01L 29/165

Abstract:

Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

US Patent:

20210280683, Sep 9, 2021

Filed:

Mar 5, 2020

Appl. No.:

16/810156

Inventors:

- Santa Clara CA, US
Rahul RAMASWAMY - Portland OR, US
Jeong Dong KIM - Scappoose OR, US
Babak FALLAHAZAD - Portland OR, US
Ting CHANG - Portland OR, US
Nidhi NIDHI - Hillsboro OR, US
Walid M. HAFEZ - Portland OR, US

International Classification:

H01L 29/423
H01L 29/06
H01L 29/66
H01L 29/165
H01L 29/10
H01L 21/02

Abstract:

Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

US Patent:

20210257452, Aug 19, 2021

Filed:

Feb 19, 2020

Appl. No.:

16/795081

Inventors:

- Santa Clara CA, US
Jeong Dong KIM - Scappoose OR, US
Walid M. HAFEZ - Portland OR, US
Rahul RAMASWAMY - Portland OR, US
Ting CHANG - Portland OR, US
Babak FALLAHAZAD - Portland OR, US

International Classification:

H01L 29/06
H01L 29/10
H01L 27/088
H01L 29/423
H01L 29/08
H01L 21/8234

Abstract:

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

US Patent:

20210257453, Aug 19, 2021

Filed:

May 5, 2021

Appl. No.:

17/308900

Inventors:

- Santa Clara CA, US
Jeong Dong KIM - Scappoose OR, US
Walid M. HAFEZ - Portland OR, US
Rahul RAMASWAMY - Portland OR, US
Ting CHANG - Portland OR, US
Babak FALLAHAZAD - Portland OR, US

International Classification:

H01L 29/06
H01L 29/423
H01L 29/10
H01L 29/08
H01L 27/088

Abstract:

Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.