Jerry A Case

US Patent:

6694489, Feb 17, 2004

Filed:

Aug 23, 2000

Appl. No.:

09/649101

Inventors:

Jerry Case - San Jose CA
Jean-Didier Allegrucci - Sunnyvale CA

Assignee:

Triscend Corporation - Mountain View CA

International Classification:

G06F 1750

US Classification:

716 1, 712 36, 716 2, 716 17, 716 18

Abstract:

A method of communicating with a configurable system-on-chip via a test interface is described. First, an interface is coupled to a configurable system-on-chip and a first command is sent to the interface from a tester. The next command execution is then blocked. Next, the first command is executed in the configurable system-on-chip. Data is then output from the configurable system-on-chip and written to a register in the interface. The data output includes a ready bit. Next, the data from the register is read. The first bit read is an asserted ready bit. The next command execution is then enabled. When the asserted ready bit is received in the tester, the tester sends a second command to the interface. The second command is then executed in the configurable system-on-a-chip.

US Patent:

6728906, Apr 27, 2004

Filed:

Aug 24, 2000

Appl. No.:

09/648297

Inventors:

Jerry Case - San Jose CA
James Murray - Mountain View CA
Jean-Didier Allegrucci - Sunnyvale CA

Assignee:

Triscend Corporation - Mountain View CA

International Classification:

G06F 1100

US Classification:

714 45, 714 30

Abstract:

An integrated circuit including a processor, a processor bus coupled to the processor, a system bus and a trace buffer. The trace buffer may capture activity on either the processor bus or the system bus.

US Patent:

6757846, Jun 29, 2004

Filed:

Nov 6, 2000

Appl. No.:

09/707318

Inventors:

James Murray - Mountain View CA
Jean-Didier Allegrucci - Sunnyvale CA
Jerry Case - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 1100

US Classification:

714 34, 710 48

Abstract:

The present invention provides a method for breakpoint stepping a multi-bus device. The multi-bus device includes a breakpoint unit capable of detecting bus events on multiple busses. The breakpoint unit is originally programmed to break on the detection of a specified bus event on a bus selected from multiple busses. After the specified bus event has been detected and the device has entered one of several possible frozen states, the breakpoint unit may be programmed to detect a new bus event on a bus selected from multiple busses. The method is repeated as needed to achieve breakpoint stepping, including single stepping.

US Patent:

6877063, Apr 5, 2005

Filed:

Dec 22, 2000

Appl. No.:

09/746815

Inventors:

Jean-Didier Allegrucci - Sunnyvale CA, US
Jerry Case - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F012/00

US Classification:

711102, 711103, 711202, 713 2, 326 38

Abstract:

A method for multiple memory aliasing for a configurable system-on-a-chip, including executing code from an internal memory, locating a configuration program in the internal memory, disabling the internal memory alias, and jumping to a secondary initialization routine, is disclosed.

US Patent:

7535254, May 19, 2009

Filed:

May 14, 2007

Appl. No.:

11/803517

Inventors:

Jerry A. Case - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/177

US Classification:

326 39, 326 41, 326 47, 710313

Abstract:

Reconfiguration of a hard macro via configuration registers is described. An integrated circuit includes configuration memory cells coupled to a hard macro via configuration registers. The configuration memory cells are for storing values for initializing the hard macro. The configuration registers are coupled to be loaded with the values stored by the configuration memory cells. Write management busing is coupled to the configuration registers for overwriting at least one of the values loaded into the configuration registers for reconfiguration of the hard macro.

US Patent:

7557607, Jul 7, 2009

Filed:

May 14, 2007

Appl. No.:

11/803522

Inventors:

Dai D. Tran - Santa Clara CA, US
Jerry A. Case - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H03K 19/177

US Classification:

326 39, 326 41

Abstract:

Reset of an interface device of an integrated circuit is described. A Peripheral Component Interconnect Express core is instantiated as an application specific circuit block in the integrated circuit. The core has a reset block configured to be in either a hierarchical reset mode or a hierarchical/separate reset mode. In the hierarchical reset mode, the reset block is configured to assert a reset signal selected of a plurality of reset signals and to automatically assert each and every other reset signal of the plurality of reset signals lower in a reset hierarchy than the reset signal selected.