Jerry Lewis

US Patent:

6338124, Jan 8, 2002

Filed:

Aug 4, 1999

Appl. No.:

09/368229

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Guy Lynn Guthrie - Austin TX
Jody B. Joyner - Austin TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711144, 711121, 711146

Abstract:

Combined response logic for a bus receives a combined data access and cast out/deallocate operation initiating by a storage device within a specific level of a storage hierarchy, with a coherency state and LRU position of the cast out/deallocate victim appended. Snoopers on the bus drive snoop responses to the combined operation with the coherency state and/or LRU position of locally-stored cache lines corresponding to the victim appended. The combined response logic determines, from the coherency state and LRU position information appended to the combined operation and the snoop responses, whether an update of the LRU position and/or coherency state of a cache line corresponding to the victim within one of the snoopers is required. If so, the combined response logic selects a snooper storage device to have at least the LRU position of a respective cache line corresponding to the victim updated, and appends an update command identifying the selected snooper to the combined response. The snooper selected to be updated may be randomly chosen, selected based on LRU position of the cache line corresponding to the victim within respective storage, or selected based on other criteria.

US Patent:

6341336, Jan 22, 2002

Filed:

Feb 17, 1998

Appl. No.:

09/024676

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1214

US Classification:

711144, 711122, 711141

Abstract:

A cache coherency protocol uses a âTaggedâ coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars.

US Patent:

6343344, Jan 29, 2002

Filed:

Aug 4, 1999

Appl. No.:

09/368221

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Guy Lynn Guthrie - Austin TX
Jody B. Joyner - Austin TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711128, 711121, 711122, 711143

Abstract:

In response to receiving a combined address for related data access and cast out operations, including an index identifying a congruence class containing both the target of the data access and the victim of the cast out, a single directory access is performed utilizing the index to locate the congruence class. Address tags within the congruence class are then compared to the address tag for the data access operation and the address tag for the cast out operation concurrently, generating separate hit signals as appropriate. Only a single directory access is required, however, rather than two separate directory accesses as required in the known art, taking advantage of the fact that both the data access target and the cast out victim belong to a single congruence class. Response latency is also improved, as is address bus bandwidth utilization.

US Patent:

6343347, Jan 29, 2002

Filed:

Aug 4, 1999

Appl. No.:

09/368224

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Guy Lynn Guthrie - Austin TX
Jody B. Joyner - Austin TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711143, 711144, 711145, 711146, 711121, 711122, 711136

Abstract:

Upon snooping a combined data access and cast out/deallocate operation initiating by a horizontal storage device, snoop logic determines appropriate responses to both the data access and the cast out/deallocate based upon the presence and coherency state of the target of the data access within a corresponding storage device, the presence and coherency state of the victim of the cast out/deallocate within the corresponding storage device, and the presence of an invalid entry within the corresponding storage device in a congruence class including both the target and the victim. The appropriate responses are âmergedâ, transmitted together in response to the combined operation as either a single response code or discrete response codes within a single response. The coherency state and LRU position of the selected victim for the cast out/deallocate portion of the combined operation may also be appended to the response to facilitate data storage management.

US Patent:

6345340, Feb 5, 2002

Filed:

Feb 17, 1998

Appl. No.:

09/024608

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711141, 711120, 711136, 711123, 711144, 711146

Abstract:

A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e. g. , DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.

US Patent:

6347361, Feb 12, 2002

Filed:

Feb 17, 1998

Appl. No.:

09/024587

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711141, 711145, 711158, 711120, 711146

Abstract:

A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e. g. , DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.

US Patent:

6347363, Feb 12, 2002

Filed:

Feb 17, 1998

Appl. No.:

09/024316

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1208

US Classification:

711150, 711122, 711138, 711168, 711146

Abstract:

Logically in line caches within a multilevel cache hierarchy are jointly controlled by single cache controller. By combining the cache controller and snoop logic for different levels within the cache hierarchy, separate queues are not required for each level. During a cache access, cache directories are looked up in parallel. Data is retrieved from an upper cache if hit, or from the lower cache if the upper cache misses and the lower cache hits. LRU units may be updated in parallel based on cache directory hits. Alternatively, the lower cache LRU unit may be updated based on cache memory accesses rather than cache directory hits, or the cache hierarchy may be provided with user selectable modes of operation for both LRU unit update schemes. The merged vertical cache controller mechanism does not require the lower cache memory to be inclusive of the upper cache memory. A novel deallocation scheme and update protocol may be implemented in conjunction with the merged vertical cache controller mechanism.

US Patent:

6349367, Feb 19, 2002

Filed:

Aug 4, 1999

Appl. No.:

09/368228

Inventors:

Ravi Kumar Arimilli - Austin TX
John Steven Dodson - Pflugerville TX
Guy Lynn Guthrie - Austin TX
Jody B. Joyner - Austin TX
Jerry Don Lewis - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

711143, 711146

Abstract:

An effectively âconditionalâ, cast out operation or cast out portion of a combined operation including a related data access may be cancelled by the combined response to the operation. The combined response logic receives coherency state and/or LRU position information for cache lines corresponding to the cast out victim within snoopers and vertically in-line storage. The combined response logic may also receive information regarding the presence of shared or invalid cache lines in snoopers or lower level storage within the congruence class for the victim, or information regarding the read-once nature of the data access target. Based on these responses, the combined response logic determines whether the cast out should be cancelled and, if so, selects and drives the appropriate combined response code.