Jerry William Pearce

US Patent:

6820182, Nov 16, 2004

Filed:

Oct 18, 2000

Appl. No.:

09/691533

Inventors:

Charles David Bauman - Sammamish WA
Richard Bealkowski - Redmond WA
Thomas J Clement - Raleigh NC
Jerry William Pearce - Apex NC
Michael Robert Turner - Carnation WA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711170, 711 5, 711114, 711117, 711120, 711124, 711167, 707204, 714 6, 714770

Abstract:

A memory exhaustion condition is handled in a data processing system having first and second regions of physical memory. The memory exhaustion condition is detected while the second region is mirroring at least part of the first region. In response to the memory exhaustion condition, memory mirroring is at least partially deactivated and at least part of the second region is utilized to augment the first region, such that the memory exhaustion condition is eliminated. In an illustrative embodiment, the data processing system compresses real memory into the first region of physical memory, and the memory exhaustion condition arises when the first region lacks sufficient available capacity to accommodate current requirements for real memory. The memory exhaustion condition is eliminated by compressing at least part of the real memory into the second region.

US Patent:

6963699, Nov 8, 2005

Filed:

Jun 3, 2004

Appl. No.:

10/859623

Inventors:

Jerry W. Pearce - Apex NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03G015/00

US Classification:

399 23, 399 16, 271 903

Abstract:

Aspects for providing an out of paper indication by a printer are described. The aspects include controlling paper ejection during a print job to provide an out of paper indication with a last sheet of a paper supply in a printer. The controlling of the paper ejection further includes starting ejection of a page of the print job, determining if the page being ejected comprises the last sheet, completing ejection of the page when the page does not comprise the last sheet, and stopping ejection of the page when the page does comprise the last sheet. Additionally, the partial ejection of the last sheet is maintained until paper is added to the paper supply.

US Patent:

7123848, Oct 17, 2006

Filed:

Jun 9, 2004

Appl. No.:

10/864183

Inventors:

Thomas J. Clement - Raleigh NC, US
Jerry W. Pearce - Apex NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03G 15/00

US Classification:

399 24, 358 114, 358 115, 399 8, 399 82

Abstract:

Aspects for managing print jobs for a printer are described. The aspects include an examination of a print queue of print jobs based on a level of consumable resources available in the printer. Further, an order of the print jobs in the printer is adjusted to prioritize printing of the print jobs that can be completely printed with the consumable resources available, wherein the printer realizes increased throughput and minimized downtime.

US Patent:

7415322, Aug 19, 2008

Filed:

Oct 24, 2006

Appl. No.:

11/585385

Inventors:

Jerry W. Pearce - Apex NC, US
Thomas J. Clement - Raleigh NC, US

Assignee:

Lenovo Singapore Pte. Ltd. - Singapore

International Classification:

G06F 1/20

US Classification:

700300, 700 19, 700 50, 710100, 713300, 361687

Abstract:

A motherboard is capable of accepting various types of fans from same or different manufacturers and is capable identifying the type of fan to which it is connected. In one embodiment, the motherboard is capable of decoding bar code data originating from a fan of the type which, rather than including circuitry for generating a single index pulse, includes an integral optical sensor and bar code pair for generating the bar code data, the motherboard being further capable of and identifying the fan based on the bar code data. Fan identification has a variety of uses including, for example, adjusting motherboard parameters to properly operate the fan based on the type of fan presently coupled to the motherboard. Additionally, fan speed may be calculated from pulses which are intended to identify the fan.

US Patent:

7532197, May 12, 2009

Filed:

Jun 22, 2004

Appl. No.:

10/873671

Inventors:

Thomas J. Clement - Raleigh NC, US
Jerry W. Pearce - Apex NC, US

Assignee:

Lenovo (Singapore) Pte Ltd. - Singapore

International Classification:

G09G 5/00

US Classification:

345156, 345 7, 715781

Abstract:

Aspects for automated monitoring of a display are described. The aspects include utilizing gaze tracking with a display to monitor attention to information on the display. Additionally, a level of alarm is escalated for the updated information when the attention by the system operator is not detected within a predetermined time period.

US Patent:

7844750, Nov 30, 2010

Filed:

Oct 24, 2006

Appl. No.:

11/585714

Inventors:

Jerry W. Pearce - Apex NC, US
Thomas J. Clement - Raleigh NC, US

Assignee:

Lenovo (Singapore) Pte. Ltd. - Singapore

International Classification:

G06F 3/00
G06F 13/12
G06F 13/38

US Classification:

710 15, 710 8, 710 62

Abstract:

A computer system is capable of operating with various types of fans from the same manufacturer or from different manufacturers and is capable identifying the type of fan which is presently installed in the system. The system includes a fan of the type which includes an integral optical sensor and detectable indicia such as, by way of example, a bar code label or imprint. Fan identification has a variety of uses including, for instance, adjusting system parameters to properly execute the computer system's cooling functions based on the type of fan presently installed, and reporting fan type and/or serial number to an administrator or central inventory server for quality control purposes. Particular embodiments include the derivation of tachometric information from the detectable indicia. The computer system may include an inventory program which maintains fan ID data for a plurality of fans.

US Patent:

59875364, Nov 16, 1999

Filed:

May 22, 1997

Appl. No.:

8/861555

Inventors:

Robert D. Johnson - Raleigh NC
Howard J. Locker - Cary NC
Jerry W. Pearce - Apex NC
Randall S. Springfield - Chapel Hill NC
Donald D. Williams - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1502

US Classification:

710 36

Abstract:

Disclosed is a personal computer system which includes a central processing unit (CPU) coupled to a direct access storage device (DASD) and a random access memory (RAM). A flash memory module is coupled to the CPU and an input/output (IO) bus and includes a basic input output system (BIOS) stored therein. The BIOS is effective for responding to the energization of the computer system by initiating a power on self test (POST). The BIOS is further operative on completion of the POST for transferring a portion of BIOS from the module to the RAM and for transferring control of the of the computer system to the BIOS portion. The portion of BIOS is operative to load a protected mode operating system (OS) into RAM and transfer control to the OS. The system further includes a logic circuit coupled to the flash memory module and the IO bus for allowing the BIOS in flash memory to be accessed while the protected mode OS is running.

US Patent:

58092919, Sep 15, 1998

Filed:

Feb 19, 1997

Appl. No.:

8/802369

Inventors:

Carlos Munoz-Bustamante - Durham NC
Jerry William Pearce - Apex NC

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 112

US Classification:

395556

Abstract:

An extended PCI bus (100) accepts both standard 33 MHz (101-102) and extended 66 MHz (103-104) PCI I/O devices, and permits the intermixing and interoperability of both types of devices on the same bus. Each extended 66 MHz initiator device (103) includes a target memory (205) that is programmed at boot up to include a list of address ranges of all extended 66 MHz devices. Each extended 66 MHz device includes a clock multiplier (202) that generates an internal 66 MHz clock signal by doubling the 33 MHz bus clock frequency. This clock multiplier may be in the form of a simple edge detecting frequency doubler (FIG. 4), or a phase locked loop (FIG. 5) that can also provide for phase adjustments to alter the skew between the bus and internal clocks. To transfer data between two extended 66 MHz devices, an extended initiator device sends, during the address/control phase of the bus cycle, a fast read or write command to the extended target device over the C/BE lines of the bus. Subsequently during the data phase of the bus cycle, data is transferred over the bus at the 66 MHz rate using the 66 MHz internal clock signals.