Jia Ling Chen

Address:

536 115 St APT A, College Point, NY 11356

Phone:

(347)7320391

VIN:

3VWLZ7AJ1BM368249

Make:

VOLKSWAGEN

Model:

JETTA

Year:

2011

Address:

6919 226 St, Oakland Gardens, NY 11364

Phone:

(646)2096828

VIN:

JTJBC1BA8A2026702

Make:

LEXUS

Model:

RX 450H

Year:

2010

US Patent:

6927454, Aug 9, 2005

Filed:

Oct 7, 2003

Appl. No.:

10/680820

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L029/76

US Classification:

257336, 257 19, 257 20, 257 24, 257192, 257213, 257344, 257392

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

7253431, Aug 7, 2007

Filed:

Feb 11, 2005

Appl. No.:

11/056456

Inventors:

Phaedon Avouris - Yorktown Heights NY, US
Jia Chen - Ossining NY, US
Christian Klinke - Ossining NY, US
Paul M. Solomon - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/06

US Classification:

257 20, 257 22, 977749, 977938

Abstract:

A method is provided for doping a carbon nanotube. The method comprises exposing the nanotube to a one-electron oxidant in a solution phase. A method is also provided for forming a carbon nanotube FET device.

US Patent:

7378336, May 27, 2008

Filed:

May 9, 2005

Appl. No.:

11/124978

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/3205

US Classification:

438592, 438593, 257413

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

7384868, Jun 10, 2008

Filed:

Sep 15, 2003

Appl. No.:

10/662900

Inventors:

Cyril Cabral, Jr. - Ossining NY, US
Roy A. Carruthers - Stormville NY, US
Jia Chen - Ossining NY, US
Christophe Detavernier - Ossining NY, US
James M. Harper - Durham NH, US
Christian Lavoie - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438682, 438597, 438683

Abstract:

A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.

US Patent:

7465649, Dec 16, 2008

Filed:

Aug 30, 2007

Appl. No.:

11/847384

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/3205

US Classification:

438592, 438593, 257413

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

7492015, Feb 17, 2009

Filed:

Nov 10, 2005

Appl. No.:

11/164109

Inventors:

Jia Chen - Ossining NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/092

US Classification:

257369, 257 40, 257E51006, 257E5104, 977742, 977940

Abstract:

Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain gates are introduced below the CNT opposite the source/drain electrodes. These source/drain gates are used to apply either a positive or negative voltage to the ends of the CNT so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. Two adjacent CNTFETs, configured such that one is an n-type CNTFET and the other is a p-type CNTFET, can be incorporated into a complementary CNT device. In order to independently adjust threshold voltage of an individual CNTFET, a back gate can also be introduced below the CNT and, particularly, below the channel region of the CNT opposite the front gate. In this manner parasitic capacitances and resistances are minimized.

US Patent:

7582534, Sep 1, 2009

Filed:

Nov 18, 2004

Appl. No.:

10/991582

Inventors:

Phaedon Avouris - Yorktown Heights NY, US
Jia Chen - Ossining NY, US
Christian Klinke - Ossining NY, US
Christopher B. Murray - Ossining NY, US
Dmitri V. Talapin - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336

US Classification:

438287, 438289, 977742, 977938

Abstract:

A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided for forming a field effect transistor comprising a nano-component that has been doped using such a dopant.

US Patent:

7598516, Oct 6, 2009

Filed:

Jan 7, 2005

Appl. No.:

11/031168

Inventors:

Phaedon Avouris - Yorktown Heights NY, US
Roy A. Carruthers - Stormville NY, US
Jia Chen - Ossining NY, US
Christophe G. M. M. Detavernier - Ghent, BE
Christian Lavoie - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/775
H01L 29/06

US Classification:

257 27, 257 9, 257347, 257E29245, 257E29168, 257E49003, 977938

Abstract:

A complementary metal oxide semiconductor (CMOS) device, e. g. , a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.