Jia Jia Lee

US Patent:

6764958, Jul 20, 2004

Filed:

Jul 28, 2000

Appl. No.:

09/627667

Inventors:

Srinivas D Nemani - San Jose CA
Li-Qun Xia - Santa Clara CA
Dian Sugiarto - Sunnyvale CA
Ellie Yieh - San Jose CA
Ping Xu - Fremont CA
Jia Lee - Campbell CA

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 2131

US Classification:

438758, 438763, 438931

Abstract:

A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

US Patent:

6777171, Aug 17, 2004

Filed:

Apr 20, 2001

Appl. No.:

09/839869

Inventors:

Ping Xu - Fremont CA
Jia Lee - Ossining NY
Ishing Lou - Santa Clara CA
Li-Qun Xia - Santa Clara CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2131

US Classification:

430322, 430311, 430313, 430317

Abstract:

A method of forming a silicon carbide layer, a silicon nitride layer, an organosilicate layer is disclosed. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a fluorine source in the presence of an electric field. The silicon nitride layer is formed by reacting a gas mixture comprising a silicon source, a nitrogen source, and a fluorine source in the presence of an electric field. The organosilicate layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, an oxygen source and a fluorine source in the presence of an electric field. The silicon carbide layer, the silicon nitride layer and the organosilicate layer are all compatible with integrated circuit fabrication processes.

US Patent:

7001850, Feb 21, 2006

Filed:

Jul 20, 2004

Appl. No.:

10/894872

Inventors:

Srinivas D Nemani - San Jose CA, US
Li-Qun Xia - Santa Clara CA, US
Dian Sugiarto - Sunnyvale CA, US
Ellie Yieh - San Jose CA, US
Ping Xu - Fremont CA, US
Jia Lee - Campbell CA, US

Assignee:

Applied Materials Inc. - Santa Clara CA

International Classification:

H01L 21/31
H01L 21/469

US Classification:

438758

Abstract:

A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

US Patent:

7117064, Oct 3, 2006

Filed:

Feb 21, 2006

Appl. No.:

11/358793

Inventors:

Srinivas D Nemani - San Jose CA, US
Li-Qun Xia - Santa Clara CA, US
Dian Sugiarto - Sunnyvale CA, US
Ellie Yieh - San Jose CA, US
Ping Xu - Fremont CA, US
Jia Lee - Campbell CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 19/00
C23C 16/00
H05H 1/24
H01L 21/31
H01L 21/469

US Classification:

700121, 427577, 42724915, 42725529, 438784

Abstract:

A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.

US Patent:

7566655, Jul 28, 2009

Filed:

Apr 5, 2006

Appl. No.:

11/398436

Inventors:

Mihaela Balseanu - Sunnyvale CA, US
Jia Lee - San Jose CA, US
Mei-Yee Shek - Mountain View CA, US
Amir Al-Bayati - San Jose CA, US
Li-Qun Xia - Santa Clara CA, US
Hichem M'Saad - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/44

US Classification:

438653, 257E21198, 257288

Abstract:

A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

US Patent:

8129290, Mar 6, 2012

Filed:

Apr 7, 2006

Appl. No.:

11/400275

Inventors:

Mihaela Balseanu - Sunnyvale CA, US
Michael S. Cox - Santa Clara CA, US
Li-Qun Xia - Santa Clara CA, US
Mei-Yee Shek - Mountain View CA, US
Jia Lee - San Jose CA, US
Vladimir Zubkov - Mountain View CA, US
Rongping Wang - Cupertino CA, US
Isabelita Roflox - Union City CA, US
Hichem M'Saad - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/31
H01L 21/469

US Classification:

438791, 257E21293

Abstract:

High tensile stress in a deposited layer such as silicon nitride, may be achieved utilizing one or more techniques, employed alone or in combination. High tensile stress may be achieved by forming a silicon-containing layer on a surface by exposing the surface to a silicon-containing precursor gas in the absence of a plasma, forming silicon nitride by exposing said silicon-containing layer to a nitrogen-containing plasma, and then repeating these steps to increase a thickness of the silicon nitride created thereby. High tensile stress may also be achieved by exposing a surface to a silicon-containing precursor gas in a first nitrogen-containing plasma, treating the material with a second nitrogen-containing plasma, and then repeating these steps to increase a thickness of the silicon nitride formed thereby. In another embodiment, tensile film stress is enhanced by deposition with porogens that are liberated upon subsequent exposure to UV radiation or plasma treatment.

US Patent:

20120196452, Aug 2, 2012

Filed:

Feb 2, 2012

Appl. No.:

13/365229

Inventors:

Mihaela Balseanu - Sunnyvale CA, US
Michael S. Cox - Davenport CA, US
Li-Qun Xia - Santa Clara CA, US
Mei-Yee Shek - Mountain View CA, US
Jia Lee - San Jose CA, US
Vladimir Zubkov - Mountain View CA, US
Rongping Wang - Cupertino CA, US
Isabelita Roflox - Union City CA, US
Hichem M'Saad - Santa Clara CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/318

US Classification:

438791, 257E21293

Abstract:

High tensile stress in a deposited layer, such as a silicon nitride layer, may be achieved utilizing one or more techniques employed either alone or in combination. In one embodiment, a silicon nitride film having high tensile stress may be formed by depositing the silicon nitride film in the presence of a porogen. The deposited silicon nitride film may be exposed to at least one treatment selected from a plasma or ultraviolet radiation to liberate the porogen. The silicon nitride film may be densified such that a pore resulting from liberation of the porogen is reduced in size, and Si—N bonds in the silicon nitride film are strained to impart a tensile stress in the silicon nitride film. In another embodiment, tensile stress in a silicon nitride film may be enhanced by depositing a silicon nitride film in the presence of a nitrogen-containing plasma at a temperature of less than about 400 C., and exposing the deposited silicon nitride film to ultraviolet radiation.