Jian N Li

US Patent:

6362684, Mar 26, 2002

Filed:

Feb 17, 2000

Appl. No.:

09/506180

Inventors:

Hans W. Klein - Danville CA
Jian Li - Portland OR
Yaohua Yang - West Linn OR

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03G 310

US Classification:

330 86, 330282

Abstract:

Provided is an amplifier circuit and method of using the same that features an adjustable resistor network to enable varying the operational characteristics of an amplifier. The resistor network includes primary resistors connected in series with a plurality of adjustment resistors connected to the output of an operational amplifier. A switching network is connected between the resistor network and the input of the operational amplifier. The switching network enables selectively varying the input and feedback resistance of the amplifier circuit to obtain a desired differential gain, while minimizing common-mode gain.

US Patent:

6376919, Apr 23, 2002

Filed:

Oct 13, 2000

Appl. No.:

09/687964

Inventors:

Jian Li - Sunnyvale CA
Paul Winer - Santa Clara CA
Adam J. DeGrush - Santa Clara CA
Steven P. Maher - Campbell CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257778, 257276, 257502, 257775, 257780, 257619, 257784

Abstract:

A method of making circuit edit structures through the backside of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the backside. Next, a polyimide layer is vapor deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the polyimide layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited polyimide layer from the backside of the integrated circuit to couple together the circuit edit connection targets. The polyimide layer may acts as both an insulation layer and an anti-reflective coating layer.

US Patent:

6461954, Oct 8, 2002

Filed:

Aug 14, 2001

Appl. No.:

09/929408

Inventors:

Jian Li - Sunnyvale CA
Xiao-Chun Mu - Saratoga CA
Sridhar Balakrishnan - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2130

US Classification:

438613, 438612, 438648, 438660, 22818022

Abstract:

Methods and apparatuses are disclosed in which a refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350Â C. to approximately 550Â C.

US Patent:

6524887, Feb 25, 2003

Filed:

Jul 20, 2001

Appl. No.:

09/909529

Inventors:

Jian Li - Sunnyvale CA
Xiao-Chun Mu - Saratogo CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438106, 438121

Abstract:

The invention relates to packaging of a novel ferroelectric polymer memory device. Packaging is configured with a recess geometry into which the ferroelectric polymer memory device extends, that resists contact with the polymer portion of the ferroelectric polymer memory device. In one embodiment, an embedded recess geometry is used that resists thermal and mechanical stresses upon the polymer. Also disclosed is a method of forming the ferroelectric polymer memory device. The method may be applied to both inorganic and organic substrates.

US Patent:

6624457, Sep 23, 2003

Filed:

Jul 20, 2001

Appl. No.:

09/909670

Inventors:

Jian Li - Sunnyvale CA
Xiao-Chun Mu - Saratogo CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 31119

US Classification:

257295, 257324, 365 8

Abstract:

The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures.

US Patent:

6756620, Jun 29, 2004

Filed:

Jun 29, 2001

Appl. No.:

09/897174

Inventors:

Jian Li - Sunnyvale CA
Xiao-Chun Mu - Saratogo CA
Mark Isenberger - Corrales NM

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2144

US Classification:

257295, 257311, 365145

Abstract:

One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

US Patent:

6798003, Sep 28, 2004

Filed:

Jul 20, 2001

Appl. No.:

09/909375

Inventors:

Jian Li - Sunnyvale CA
Xiao-Chun Mu - Saratogo CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 4700

US Classification:

257295, 438 3, 438 6, 438253, 438396, 438939

Abstract:

A polymer memory device includes two organic adhesion layers that facilitate an integral package comprising a lower and an upper electrode and the ferroelectric polymer memory structure. The ferroelectric polymer memory structure includes crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure includes spin-on and/or Langmuir-Blodgett deposited compositions. A memory system allows the polymer memory device to interface with various existing hosts.

US Patent:

6858862, Feb 22, 2005

Filed:

Jun 29, 2001

Appl. No.:

09/896656

Inventors:

Jian Li - Sunnyvale CA, US
Xiao-Chun Mu - Saratoga CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L029/06

US Classification:

257 10, 257295, 257314, 438 3, 438 99, 438407

Abstract:

The invention relates to discrete, spaced-apart ferroelectric polymer memory device embodiments. The ferroelectric polymer memory device is fabricated by spin-on polymer processing and etching using photolithographic technology. The size of the discrete, spaced-apart ferroelectric polymer structures may be tied to a specific photolithography minimum feature dimension. The invention also relates to a process for making embodiments of a polymer memory device that includes discrete, spaced-apart ferroelectric polymer structures. The discrete, spaced-apart ferroelectric polymer structures may have a minimum feature that is tied to the current photolithography that may reduce the voltage and increase the switching speed.