Jian C Wu

US Patent:

8034457, Oct 11, 2011

Filed:

Nov 13, 2008

Appl. No.:

12/270247

Inventors:

Jian Wu - Fremont CA, US
Craig Stringer - DuBois PA, US
Sundeep Kumar - Bangalore, IN

International Classification:

B32B 17/06
C03C 8/00

US Classification:

428428, 428688, 501 14, 501 15, 501 17, 501 21, 501 55, 501 65, 501 66, 501 68

Abstract:

A seal structure is provided for an energy storage device. The seal structure includes a sealing glass joining an ion-conducting first ceramic to an electrically insulating second ceramic. The sealing glass has a composition that includes about 48 weight percent silica, about 20 weight percent to about 25 weight percent boria, about 20 weight percent to about 24 weight percent alumina, and about 8 weight percent to about 12 weight percent sodium oxide based on the total weight of the sealing glass composition. A method for making the seal structure is provided. An article comprising the seal structure is also provided.

US Patent:

20100120602, May 13, 2010

Filed:

Nov 13, 2008

Appl. No.:

12/270258

Inventors:

Jian Wu - Fremont CA, US
Mamatha Nagesh - Shimoga, IN
Sundeep Kumar - Bangalore, IN
Craig Stringer - DuBois PA, US
Digamber Porob - Moira, IN
Vinayak Hassan Vishwanath - Bangalore, IN

International Classification:

C03C 8/02

US Classification:

501 21

Abstract:

A sealing glass for an energy storage device is provided. The sealing glass includes silicon dioxide, boron oxide, aluminum oxide, sodium oxide and zirconium oxide. Methods for preparing the sealing glass and the energy storage device incorporating the sealing glass are also provided.

US Patent:

20130043452, Feb 21, 2013

Filed:

Aug 15, 2011

Appl. No.:

13/210342

Inventors:

Rene Meyer - Atherton CA, US
Jian Wu - San Jose CA, US
Julie Casperson Brewer - Santa Clara CA, US

Assignee:

UNITY SEMICONDUCTOR CORPORATION - SUNNYVALE CA

International Classification:

H01L 45/00
H01L 21/8239

US Classification:

257 4, 438382, 257E45001, 257E21645, 257E21004

Abstract:

Structures and methods to enhance cycling endurance of BEOL memory elements are disclosed. In some embodiments, a memory element can include a support layer having a smooth and planar upper surface as deposited or as created by additional processing. A first electrode is formed the smooth and planar upper surface. The support layer can be configured to influence the formation of the first electrode to determine a substantially smooth surface of the first electrode. The memory element is formed over the first electrode having the substantially smooth surface, the memory element including one or more layers of an insulating metal oxide (IMO) operative to exchange ions to store a plurality of resistive states. The substantially smooth surface of the first electrode provides for uniform current densities through unit cross-sectional areas of the IMO. The memory element can include one or more layers of a conductive metal oxide (CMO).

US Patent:

20180151386, May 31, 2018

Filed:

Nov 7, 2017

Appl. No.:

15/805857

Inventors:

- Fremont CA, US
Sangjun CHO - San Ramon CA, US
Steven CHUANG - San Francisco CA, US
Jian WU - Fremont CA, US

International Classification:

H01L 21/311
H01L 21/033
H01L 21/027
H01L 21/02

Abstract:

A method for etching an organic carbon based layer below a silicon containing hardmask is provided. An etch gas is provided comprising oxygen and a halogen containing component, and a passivation component, wherein a ratio by volume of total flow rate of the etch gas to flow rate of the halogen containing component is between 10,000:1 to 10:1. The etch gas is formed into a plasma, wherein the organic carbon based layer and the silicon contain hardmask are exposed to the plasma and wherein the plasma selectively etches the organic carbon based layer with respect to the silicon containing hardmask.