Jian Jun Yu

US Patent:

8017483, Sep 13, 2011

Filed:

Jun 29, 2009

Appl. No.:

12/493549

Inventors:

Gregory G. Freeman - Hopewell Junction NY, US
Shreesh Narasimha - Hopewell Junction NY, US
Ning Su - Hopewell Junction NY, US
Hasan M. Nayfeh - Hopewell Junction NY, US
Nivo Rovedo - Hopewell Junction NY, US
Werner A. Rausch - Hopewell Junction NY, US
Jian Yu - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336

US Classification:

438286, 438525, 257E21345, 257E21618

Abstract:

The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.

US Patent:

8569810, Oct 29, 2013

Filed:

Dec 7, 2010

Appl. No.:

12/961553

Inventors:

Jian Yu - Danbury CT, US
Jeffrey B. Johnson - Essex Junction VT, US
Zhengwen Li - Danbury CT, US
Chengwen Pei - Danbury CT, US
Michael Hargrove - Clinton Corners NY, US

Assignee:

International Business Machines Corporation - Armonk NY
GLOBALFOUNDRIES, Inc. - Grand Cayman

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119

US Classification:

257288, 257E21409, 257E29255

Abstract:

A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

US Patent:

8592266, Nov 26, 2013

Filed:

Oct 27, 2010

Appl. No.:

12/912963

Inventors:

Zhengwen Li - Danbury CT, US
Dechao Guo - Wappingers Falls NY, US
Randolph F. Knarr - Putnam Valley NY, US
Chengwen Pei - Danbury CT, US
Gan Wang - Fishkill NY, US
Yanfeng Wang - Fishkill NY, US
Keith Kwong Hon Wong - Wappingers Falls NY, US
Jian Yu - Danbury CT, US
Jun Yuan - Fishkill NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/336
H01L 21/8234

US Classification:

438197, 438270, 257288, 257330

Abstract:

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

US Patent:

8643122, Feb 4, 2014

Filed:

Dec 6, 2012

Appl. No.:

13/707058

Inventors:

Viraj Y. Sardesai - Hopewell Junction NY, US
Cung D. Tran - Newburgh NY, US
Jian Yu - Danbury CT, US
Reinaldo A. Vega - Wappingers Falls NY, US
Rajasekhar Venigalla - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/417
H01L 29/45
H01L 29/772

US Classification:

257408, 257E29116, 257E29271

Abstract:

A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

US Patent:

20120119302, May 17, 2012

Filed:

Nov 11, 2010

Appl. No.:

12/944018

Inventors:

Chengwen Pei - Danbury CT, US
Jeffrey B. Johnson - Essex Junction VT, US
Zhengwen Li - Danbury CT, US
Jian Yu - Danbury CT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/532
H01L 21/28
H01L 29/78

US Classification:

257382, 257754, 438586, 257E23155, 257E29255, 257E2119

Abstract:

An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer.An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

US Patent:

20120187460, Jul 26, 2012

Filed:

Jan 25, 2011

Appl. No.:

13/013081

Inventors:

Christian Lavoie - Ossining NY, US
Zhengwen Li - Danbury CT, US
Ahmet S. Ozcan - Pleasantville NY, US
Filippos Papadatos - Wappingers Falls NY, US
Chengwen Pei - Danbury CT, US
Jian Yu - Danbury CT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78
H01L 21/336

US Classification:

257288, 438293, 257E29271, 257E21425

Abstract:

A method of forming a semiconductor device is provided that includes forming a first metal semiconductor alloy on a semiconductor containing surface, forming a dielectric layer over the first metal semiconductor alloy, forming an opening in the dielectric layer to provide an exposed surface the first metal semiconductor alloy, and forming a second metal semiconductor alloy on the exposed surface of the first metal semiconductor alloy. In another embodiment, the method includes forming a gate structure on a channel region of a semiconductor substrate, forming a dielectric layer over at least a source region and a drain region, forming an opening in the dielectric layer to provide an exposed surface the semiconductor substrate, forming a first metal semiconductor alloy on the exposed surface of the semiconductor substrate, and forming a second metal semiconductor alloy on the first metal semiconductor alloy.

US Patent:

20130171795, Jul 4, 2013

Filed:

Feb 21, 2013

Appl. No.:

13/772954

Inventors:

International Business Machines Corporation - Armonk NY, US
Jeffrey B. Johnson - Essex Junction VT, US
Zhengwen Li - Danbury CT, US
Jian Yu - Danbury CT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/768

US Classification:

438303

Abstract:

An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer.An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

US Patent:

20130175641, Jul 11, 2013

Filed:

Feb 28, 2013

Appl. No.:

13/780877

Inventors:

International Business Machines Corporation - Armonk NY, US
Dechao Guo - Wappinger Falls NY, US
Randolph F. Knarr - Albany NY, US
Chengwen Pei - Danbury CT, US
Gan Wang - Fishkill NY, US
Yanfeng Wang - Fishkill NY, US
Keith Kwong Hon Wong - Wappingers Falls NY, US
Jian Yu - Danbury CT, US
Jun Yuan - San Diego CA, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 29/78

US Classification:

257410

Abstract:

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function metal portion to form a gate structure that enhances performance of a replacement gate field effect transistor.