Jian Ping Li

US Patent:

6362684, Mar 26, 2002

Filed:

Feb 17, 2000

Appl. No.:

09/506180

Inventors:

Hans W. Klein - Danville CA
Jian Li - Portland OR
Yaohua Yang - West Linn OR

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03G 310

US Classification:

330 86, 330282

Abstract:

Provided is an amplifier circuit and method of using the same that features an adjustable resistor network to enable varying the operational characteristics of an amplifier. The resistor network includes primary resistors connected in series with a plurality of adjustment resistors connected to the output of an operational amplifier. A switching network is connected between the resistor network and the input of the operational amplifier. The switching network enables selectively varying the input and feedback resistance of the amplifier circuit to obtain a desired differential gain, while minimizing common-mode gain.

US Patent:

6376919, Apr 23, 2002

Filed:

Oct 13, 2000

Appl. No.:

09/687964

Inventors:

Jian Li - Sunnyvale CA
Paul Winer - Santa Clara CA
Adam J. DeGrush - Santa Clara CA
Steven P. Maher - Campbell CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2348

US Classification:

257778, 257276, 257502, 257775, 257780, 257619, 257784

Abstract:

A method of making circuit edit structures through the backside of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the backside. Next, a polyimide layer is vapor deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the polyimide layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited polyimide layer from the backside of the integrated circuit to couple together the circuit edit connection targets. The polyimide layer may acts as both an insulation layer and an anti-reflective coating layer.

US Patent:

6461954, Oct 8, 2002

Filed:

Aug 14, 2001

Appl. No.:

09/929408

Inventors:

Jian Li - Sunnyvale CA
Xiao-Chun Mu - Saratoga CA
Sridhar Balakrishnan - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2130

US Classification:

438613, 438612, 438648, 438660, 22818022

Abstract:

Methods and apparatuses are disclosed in which a refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350Â C. to approximately 550Â C.

US Patent:

6509998, Jan 21, 2003

Filed:

Jun 7, 2001

Appl. No.:

09/877367

Inventors:

Liji Huang - San Jose CA
Jian Li - Sunnyvale CA
Naiqian Han - Sunnyvale CA
James Yang - Stanford CA

Assignee:

INTPAX, Inc. - Cupertino CA

International Classification:

G02F 103

US Classification:

359245, 359247, 359248, 359290, 359291, 372 12, 372 20, 372 43

Abstract:

A conductive substrate supports an array of multi-channel optical attenuating devices. Each attenuating device includes a membrane with an optically transparent portion And a flexible support for positioning the optically transparent portion of the membrane spaced from the substrate for defining an air gap. The air gap constitutes a cross-shaped gap-chamber having a horizontally and vertically elongated chambers extended from a central intersection area functioning as an optical active area. A voltage bias circuit applies an electrical bias between the conductive substrate and the membrane to adjust and control an air-gap thickness at the optical active area between the conductive substrate and the membrane. Each of the devices can be manufactured on the same silicon wafer using the same process and can be individually controlled to accommodate different wavelength attenuation at each channel. Production costs, and time and efforts required for aligning the array to optical fibers are also reduced.

US Patent:

6524887, Feb 25, 2003

Filed:

Jul 20, 2001

Appl. No.:

09/909529

Inventors:

Jian Li - Sunnyvale CA
Xiao-Chun Mu - Saratogo CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438106, 438121

Abstract:

The invention relates to packaging of a novel ferroelectric polymer memory device. Packaging is configured with a recess geometry into which the ferroelectric polymer memory device extends, that resists contact with the polymer portion of the ferroelectric polymer memory device. In one embodiment, an embedded recess geometry is used that resists thermal and mechanical stresses upon the polymer. Also disclosed is a method of forming the ferroelectric polymer memory device. The method may be applied to both inorganic and organic substrates.

US Patent:

6583652, Jun 24, 2003

Filed:

May 30, 2002

Appl. No.:

10/159009

Inventors:

Hans W. Klein - San Jose CA
Jian Li - Portland OR
Paul Hildebrant - Banks OR

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 522

US Classification:

327103, 327 65, 330254

Abstract:

An improved programmable transconductor can be efficiently implemented utilizing a programmable resistor circuit that allows for only a selected portion of the resistor circuit (associated with a desired transconductor gain) to be coupled between summing nodes of the transconductor. Additional switching circuits can be used to reduce gain errors associated with the switches used to implement the aforementioned solution. Additionally, the improved programmable transconductor can be integrated into fully differential programmable analog integrated circuits, thereby enhancing the performance of such integrated circuits.

US Patent:

6586822, Jul 1, 2003

Filed:

Sep 8, 2000

Appl. No.:

09/658819

Inventors:

Quat T. Vu - Santa Clara CA
Jian Li - Sunnyvale CA
Qing Ma - San Jose CA
Maria V. Henao - Pleasanton CA
Xiao-Chun Mu - Saratoga CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2302

US Classification:

257678, 438100, 438106, 438108, 438109, 438113, 438127, 174524

Abstract:

A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

US Patent:

6624457, Sep 23, 2003

Filed:

Jul 20, 2001

Appl. No.:

09/909670

Inventors:

Jian Li - Sunnyvale CA
Xiao-Chun Mu - Saratogo CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 31119

US Classification:

257295, 257324, 365 8

Abstract:

The present invention relates to a ferroelectric polymer storage device including at least two stacked ferroelectric polymer memory structures that are arrayed next to at least two respective stacked topologies that are a pre-fabricated silicon substrate cavity that includes interlayer dielectric layers and via structures.