Jie Fang

US Patent:

7515076, Apr 7, 2009

Filed:

Sep 28, 2007

Appl. No.:

11/864876

Inventors:

Rahul Singh - Austin TX, US
Prashanth Drakshapalli - Austin TX, US
Jie Fang - Austin TX, US
Edwin De Angel - Austin TX, US
Mohit Sood - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H03M 1/00

US Classification:

341122, 341123, 341155

Abstract:

A method and apparatus for reducing switching noise in a system-on-chip (SoC) integrated circuit including an analog to digital converter (ADC) provides for reduced noise in the ADC conversions. Sampling circuits of the ADC are operated by sampling clock signals and digital circuits and other noise-generating circuits such as power converters, are operated by digital circuit clock signals. Both sets of clock signals are derived from the same master clock by a clock generator circuit, but an offset is applied in the clock generator circuit to move the edges of the digital circuit clock signals away from critical sampling intervals corresponding to edges of the sampling clocks. In one embodiment, the offset is applied by a processor core that forms part of the digital circuits by setting a value in the clock generator, which the clock generator then loads into the divider after halting the clock to the digital circuits.