Jin Young Han

US Patent:

20200167402, May 28, 2020

Filed:

Nov 23, 2018

Appl. No.:

16/198945

Inventors:

- Armonk NY, US
Paul SOLOMON - Westchester NY, US
Xiaodong CUI - Chappaqua NY, US
Jin Ping HAN - Yorktown Heights NY, US
Xin ZHANG - Yorktown Heights NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 17/10
G06F 9/30
G06F 9/38
G06K 9/62
G06N 3/08

Abstract:

Embodiments for implementing a softmax function in an analog circuit. The analog circuit may comprise a plurality of input nodes to accept voltage inputs; a plurality of diodes connected to each of the plurality of input nodes to perform a current adding function; a log amplifier coupled to the plurality of diodes; a plurality of analog adders coupled to the voltage inputs and an output of the log amplifier; and a plurality of exponential amplifiers, each of the plurality of exponential amplifiers coupled to one of the plurality of analog adders.

US Patent:

20200005129, Jan 2, 2020

Filed:

Jun 28, 2018

Appl. No.:

16/021824

Inventors:

- Armonk NY, US
Martin M. Frank - Dobbs Ferry NY, US
JIN PING HAN - Yorktown Heights NY, US

International Classification:

G06N 3/063
G06N 3/08

Abstract:

Described herein is a crossbar array that includes a cross-point synaptic device at each of a plurality of crosspoints. The cross-point synaptic device includes a weight storage element comprising a set of nanocrystal dots. Further, the cross-point synaptic device includes at least three terminals for interacting with the weight storage element, wherein a weight is stored in the weight storage element by sending a first electric pulse via a gate terminal from the at least three terminals, the first electric pulse causes the nanocrystal dots to store a corresponding charge, and the weight is erased from the weight storage element by sending a second electric pulse via the gate terminal, the second electric pulse having an opposite polarity of the first electric pulse.

US Patent:

20190326387, Oct 24, 2019

Filed:

Jul 3, 2019

Appl. No.:

16/502783

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Xiao Sun - Pleasantville NY, US
Jin Ping Han - Yorktown Heights NY, US
Vijay Narayanan - New York NY, US

International Classification:

H01L 49/02
H01B 3/10
H01L 27/11507
H01L 21/02
H01L 21/3213
H01L 21/283

Abstract:

Artificial synaptic devices with an HfO-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400 C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

US Patent:

20190252499, Aug 15, 2019

Filed:

Apr 25, 2019

Appl. No.:

16/395024

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Xiao Sun - Pleasantville NY, US
Jin Ping Han - Yorktown Heights NY, US
Vijay Narayanan - New York NY, US

International Classification:

H01L 29/12
H01L 23/52
H01L 29/06
H01L 27/085

Abstract:

Artificial synaptic devices with a HfO-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO-based material. A FET device formed by the present techniques is also provided.

US Patent:

20190252500, Aug 15, 2019

Filed:

Apr 25, 2019

Appl. No.:

16/395084

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Xiao Sun - Pleasantville NY, US
Jin Ping Han - Yorktown Heights NY, US
Vijay Narayanan - New York NY, US

International Classification:

H01L 29/12
H01L 23/52
H01L 29/06
H01L 27/085

Abstract:

Artificial synaptic devices with a HfO-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO-based material. A FET device formed by the present techniques is also provided.

US Patent:

20190131383, May 2, 2019

Filed:

Oct 30, 2017

Appl. No.:

15/797848

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Xiao Sun - Pleasantville NY, US
Jin Ping Han - Yorktown Heights NY, US
Vijay Narayanan - New York NY, US

International Classification:

H01L 49/02
H01L 27/11507
H01B 3/10
H01L 21/02
H01L 21/283
H01L 21/3213

Abstract:

Artificial synaptic devices with an HfO-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400 C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

US Patent:

20190131407, May 2, 2019

Filed:

Oct 30, 2017

Appl. No.:

15/797774

Inventors:

- Armonk NY, US
Takashi Ando - Tuckahoe NY, US
Xiao Sun - Pleasantville NY, US
Jin Ping Han - Yorktown Heights NY, US
Vijay Narayanan - New York NY, US

International Classification:

H01L 29/12
H01L 23/52
H01L 27/085
H01L 29/06

Abstract:

Artificial synaptic devices with a HfO-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO-based material. A FET device formed by the present techniques is also provided.