Jin Lu

US Patent:

7754612, Jul 13, 2010

Filed:

Mar 14, 2007

Appl. No.:

11/686079

Inventors:

Jin Lu - Manassas VA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438692, 257E21224, 257E21228, 257E2123, 257E21307, 438690, 438753

Abstract:

Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other.

US Patent:

8071480, Dec 6, 2011

Filed:

Jun 17, 2010

Appl. No.:

12/818019

Inventors:

Jin Lu - Manassas VA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438692, 257E21224, 257E21228, 257E2123, 257E21307, 438690, 438753

Abstract:

Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other.

US Patent:

20120244705, Sep 27, 2012

Filed:

Mar 23, 2011

Appl. No.:

13/069408

Inventors:

Hongqi LI - Boise ID, US
ANURAG JINDAL - Boise ID, US
Jin Lu - Boise ID, US

International Classification:

H01L 21/306
C11D 7/26

US Classification:

438692, 510175, 257E2123

Abstract:

A post-W CMP cleaning solution consists of carboxylic acid and deionized water. The carboxylic acid may be selected from the group consisting of (1) monocarboxylic acids; (2) dicarboxylic acids; (3) tricarboxylic acids; (4) polycarboxylic acids; (5) hydroxycarboxylic acids; (6) salts of the above-described carboxylic acids; and (7) any combination thereof. The post-W CMP cleaning solution can work well without adding any other chemical additives such as surfactants, corrosion inhibitors, pH adjusting agents or chelating agents.

US Patent:

20130313718, Nov 28, 2013

Filed:

May 24, 2012

Appl. No.:

13/480341

Inventors:

Sony Varghese - Boise ID, US
Andrew Carswell - Boise ID, US
Kozaburo Sakai - Boise ID, US
Andrey V. Zagrebelny - Eagan MN, US
Wayne Huang - Boise ID, US
Jin Lu - Boise ID, US
Suresh Ramakrishnan - Boise ID, US

Assignee:

MICRON TECHNOLOGY, INC. - Boise ID

International Classification:

H01L 23/498
H01L 21/66
H01L 21/768

US Classification:

257774, 438667, 438 16, 257E23067, 257E2153, 257E21577

Abstract:

A method of processing a substrate having integrated circuitry includes forming through-substrate vias partially through the substrate from a first side of the substrate. At least one through-substrate structure is formed partially through the substrate from the first substrate side. The at least one through-substrate structure extends deeper into the substrate than do the through-substrate vias. Substrate material is removed from a second side of the substrate to expose the through-substrate vias and the at least one through-substrate structure on the second substrate side. Additional implementations are disclosed. Integrated circuit substrates are disclosed independent of method of manufacture.

US Patent:

20210408039, Dec 30, 2021

Filed:

Sep 7, 2021

Appl. No.:

17/468170

Inventors:

- Boise ID, US
Ramey M. Abdelrahaman - Boise ID, US
Silvia Borsari - Boise ID, US
Chris M. Carlson - Nampa ID, US
David Daycock - Woodhaven, SG
Matthew J. King - Boise ID, US
Jin Lu - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 27/11582
G11C 5/06
H01L 27/11556
H01L 27/1157
H01L 23/522
H01L 27/11524

Abstract:

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

US Patent:

20210111184, Apr 15, 2021

Filed:

Oct 15, 2019

Appl. No.:

16/653062

Inventors:

- Boise ID, US
Ramey M. Abdelrahaman - Boise ID, US
Silvia Borsari - Boise ID, US
Chris M. Carlson - Nampa ID, US
David Daycock - Woodhaven, SG
Matthew J. King - Boise ID, US
Jin Lu - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 27/11582
G11C 5/06
H01L 27/11524
H01L 27/1157
H01L 23/522
H01L 27/11556

Abstract:

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. A wall is formed in individual of the trenches laterally-between immediately-laterally-adjacent of the memory-block regions. The forming of the wall comprises lining sides of the trenches with insulative material comprising at least one of an insulative nitride and elemental-form boron. A core material is formed in the trenches to span laterally-between the at least one of the insulative nitride and the elemental-form boron. Structure independent of method is disclosed.

US Patent:

20200235007, Jul 23, 2020

Filed:

Jan 27, 2020

Appl. No.:

16/773716

Inventors:

- Boise ID, US
Anurag Jindal - Boise ID, US
Jin Lu - Boise ID, US
Shyam Ramalingam - Boise ID, US

International Classification:

H01L 21/768
H01L 23/48
H01L 21/288

Abstract:

Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

US Patent:

20180204803, Jul 19, 2018

Filed:

Jan 13, 2017

Appl. No.:

15/405711

Inventors:

- Boise ID, US
Mikhail A. Treger - Boise ID, US
Jin Lu - Boise ID, US

International Classification:

H01L 23/532
H01L 23/48
H01L 21/768

Abstract:

Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a conductive material at least partially filling an opening in a semiconductor substrate, and a nitrided barrier between the conductive material and a sidewall in the opening. The nitrided barrier comprises a nitride material and a barrier material, such as tantalum, between the nitride material and the sidewall of the substrate.