Jin Lu

US Patent:

7409622, Aug 5, 2008

Filed:

Nov 10, 2005

Appl. No.:

11/272265

Inventors:

Jin Lu - Lafayette CO, US
Keith G. Boyer - Broomfield CO, US

Assignee:

Storage Technology Corporation - Louisville CO

International Classification:

H03M 13/00

US Classification:

714755, 714790, 714795, 714746, 714780, 714784, 375262, 375341

Abstract:

A system and method for Reverse Error Correction Coding. The system includes a Constraint encoder, an Error Correction Code encoder, and a uniform interleaver. The Constraint encoder receives a source data stream and generates a first intermediate encoded data stream satisfying a first predetermined timing data constraint. The Error Correction Code encoder receives the first intermediate encoded data stream and generates a second intermediate encoded data stream having one or more Error Correction Code based elements. The uniform interleaver receives the second intermediate encoded data stream and generates a channel data stream having the one or more Error Correction Code based elements and satisfying a second predetermined timing data constraint.

US Patent:

8006172, Aug 23, 2011

Filed:

Jul 10, 2007

Appl. No.:

11/775748

Inventors:

Keith G. Boyer - Broomfield CO, US
Jin Lu - Lafayette CO, US
Mark Hennecken - Denver CO, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

H03M 13/03
G06F 11/00

US Classification:

714786, 714800

Abstract:

A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder. Converged data from the auxiliary decoder replaces otherwise null data stored in the block matrix memory.

US Patent:

8316281, Nov 20, 2012

Filed:

Nov 3, 2009

Appl. No.:

12/611326

Inventors:

Richard A. Gill - Arvada CO, US
Jin Lu - Lafayette CO, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 11/00

US Classification:

714771

Abstract:

An LDPC coding system includes a number of LDPC encoders and a number of LDPC decoders. The number of encoders/decoders is between one and one fewer than the total number of tracks on the high density tape are provided. The LDPC encoders are operable to break data from an incoming data sector into the data blocks to be written to the high density tape. The LDPC decoders are operable to assemble the data blocks into data sectors.

US Patent:

8413014, Apr 2, 2013

Filed:

Jul 29, 2009

Appl. No.:

12/511664

Inventors:

Jin Lu - Lafayette CO, US
Keith G. Boyer - Broomfield CO, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G11C 29/42
G11C 29/00

US Classification:

714763, 714758, 714769, 714771, 714752, 360 26, 36518509, 369 3021, 369 3022

Abstract:

A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.

US Patent:

8630053, Jan 14, 2014

Filed:

Feb 14, 2012

Appl. No.:

13/372600

Inventors:

Shaohua Yang - Santa Clara CA, US
Jin Lu - Lafayette CO, US
Haitao Xia - San Jose CA, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

G11B 5/09

US Classification:

360 65, 360 25, 360 31

Abstract:

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: a buffer circuit, an equalizer circuit, a data processing circuit, and a retry determination circuit. The buffer is operable to store digital samples as a buffered output, and the equalizer circuit is operable to equalize the buffered output using a first equalization target to yield a first equalized output, and to yield a second equalized output using a second equalization target. The retry determination circuit is operable to select the second equalization target based at least in part on an occurrence of an error.

US Patent:

20130235920, Sep 12, 2013

Filed:

Mar 8, 2012

Appl. No.:

13/415326

Inventors:

Shaohua Yang - Santa Clara CA, US
Jin Lu - Lafayette CO, US

International Classification:

H04L 27/01

US Classification:

375229

Abstract:

The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.

US Patent:

20130332790, Dec 12, 2013

Filed:

Jun 7, 2012

Appl. No.:

13/491062

Inventors:

Jin Lu - Lafayette CO, US
Shaohua Yang - San Jose CA, US

International Classification:

H03M 13/11
G06F 11/10
H03M 13/23

US Classification:

714752, 714786, 714E11032

Abstract:

The present inventions are related to LDPC decision-driven equalizer adaptation. For example, a data processing apparatus is disclosed that includes an equalizer operable to yield equalized data, a low density parity check decoder operable to decode the equalized data to yield decoded data, and an equalizer adaptation circuit operable to adapt settings in the equalizer based in part on the decoded data.

US Patent:

20150243310, Aug 27, 2015

Filed:

Mar 18, 2014

Appl. No.:

14/217805

Inventors:

- San Jose CA, US
Richard Rauschmayer - Longmont CO, US
Jin Lu - Lafayette CO, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

G11B 5/48

Abstract:

Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.

Address:

558 Jackson St, Lafayette, CO 80026

VIN:

1FAHP28137G100012

Make:

FORD

Model:

HP28

Year:

2007