Jing S Yang

US Patent:

20090119410, May 7, 2009

Filed:

Nov 28, 2008

Appl. No.:

12/325103

Inventors:

Jing Yang - San Ramon CA, US
Quan Wang - Beijing, CN
Michael Ma - Fremont CA, US
Meichun Zhang - Nanshan Shenzhen, CN

Assignee:

UTSTARCOM, INC. - Alameda CA

International Classification:

G06F 15/16

US Classification:

709231

Abstract:

A media content distribution system for distributed multimedia streaming communicates over a network and incorporates multiple independent media stations, each having a media director for control and a number of media engines for storage, retrieval and streaming of media content. A middleware system employing a execution engine for service platform middleware and a presentation engine for terminal middleware is provided for flexible interfacing with network transport and home network elements respectively and the IPTV applications supported.

US Patent:

20220413707, Dec 29, 2022

Filed:

Aug 29, 2022

Appl. No.:

17/898474

Inventors:

- Suwon-si, KR
Jing YANG - San Jose CA, US
Rekha PITCHUMANI - Oak Hill VA, US

International Classification:

G06F 3/06
G06F 16/174
G06F 12/06

Abstract:

A storage device is disclosed. The storage device may include storage for data. A host interface logic may receive a dataset and a logical address from a host. A stream assignment logic may assign a stream identifier (ID) to a compressed dataset based on a compression characteristic of the compressed dataset. The stream ID may be one of at least two stream IDs; the compressed dataset may be determined based on the dataset. A logical-to-physical translation layer may map the logical address to a physical address in the storage. A controller may store the compressed dataset at the physical address using the stream ID.

US Patent:

20220374152, Nov 24, 2022

Filed:

Mar 14, 2022

Appl. No.:

17/694657

Inventors:

- Suwon-si, KR
Jing YANG - San Jose CA, US
Marie Mai NGUYEN - Pittsburg PA, US
Mehran ELYASI - Saint Paul MN, US
Rekha PITCHUMANI - Oak Hill VA, US

International Classification:

G06F 3/06

Abstract:

A storage unit is disclosed. The storage unit may include storage for a component codeword. The component codeword may be stored in a block in the storage. The block may also store a block codeword. An interface may receive a read request for a chunk of data from a host and may send the chunk of data to the host. A circuit may read the component codeword from the block in the storage. An error correcting code (ECC) decoder may determine the chunk of data based at least in part on the component codeword.

US Patent:

20220374260, Nov 24, 2022

Filed:

Mar 3, 2022

Appl. No.:

17/686404

Inventors:

- Suwon-si, KR
Jing YANG - San Jose CA, US
Rekha PITCHUMANI - Herndon VA, US

International Classification:

G06F 9/48
G06F 9/54
G06F 9/455

Abstract:

A method for computation may include performing a first computation using a first system, wherein the first computation may be based, at least in part, on a first computation basis, performing a second computation using a second system, wherein the second computation may be based, at least in part, on a second computation basis, and coordinating the first computation and the second computation. The first computation basis may include a clock basis, and the second computation basis may include an event basis. The first computation may include a first operation, the second computation may include a second operation, and the coordinating the first computation and the second computation may include coordinating the first computation and the second computation based on the first operation and the second operation. The first operation may include an application computation operation, and the second operation may include a device computation operation.

US Patent:

20230089812, Mar 23, 2023

Filed:

Nov 16, 2021

Appl. No.:

17/528030

Inventors:

- Suwon-si, KR
Jing Yang - San Jose CA, US
Rekha Pitchumani - Oak Hill VA, US

International Classification:

G06F 9/50

Abstract:

Workload distribution in a system including a non-volatile memory device is disclosed. A request is received including an address associated with a memory location of the non-volatile memory device. A hash value is calculated based on the address. A list of node values is searched, and one of the node values in the list is identified based on the hash value. A processor is identified based on the one of the node values, and the address is stored in association with the processor. The request is transmitted to the processor for accessing the memory location.

US Patent:

20200021362, Jan 16, 2020

Filed:

Sep 17, 2019

Appl. No.:

16/573916

Inventors:

- Sunnyvale CA, US
Jingyun Zou - Sunnyvale CA, US
Jing Yang - Sunnyvale CA, US

International Classification:

H04B 10/25
H04B 10/079
H04J 14/02
H04B 10/69
H04B 10/077

Abstract:

A system may include a first module at a far end, and an optical fiber coupled to the first module. The system may also include a second module at a near end that is configured to generate and transmit instructions to the first module to control operation of the first module.

US Patent:

20170366266, Dec 21, 2017

Filed:

Jun 16, 2017

Appl. No.:

15/624864

Inventors:

- Sunnyvale CA, US
Jingyun Zou - Sunnyvale CA, US
Jing Yang - Sunnyvale CA, US

International Classification:

H04B 10/25
H04J 14/02
H04B 10/079

Abstract:

A system may include a first module at a far end, and an optical fiber coupled to the first module. The system may also include a second module at a near end that is configured to generate and transmit instructions to the first module to control operation of the first module.

US Patent:

20140176359, Jun 26, 2014

Filed:

Dec 20, 2012

Appl. No.:

13/722388

Inventors:

- Irvine CA, US
Xinyu Yu - San Jose CA, US
Jing Yang - Fremont CA, US
Sumant Ranganathan - Saratoga CA, US

Assignee:

BROADCOM CORPORATION - Irvine CA

International Classification:

H03M 1/12

US Classification:

341172

Abstract:

An analog-to-digital converter (ADC) includes reference charge cancellation features to at least partially offset a voltage distortion on a bypass capacitor of a reference buffer due to a voltage reference hit taken by a switched capacitor bank with which the bypass capacitor is connected. The charge cancellation may be configured in logic to be input signal dependent because different resolved bits or transitions between resolved bits may cause different amounts of voltage reference hits. By adjusting the bypass capacitor in response to each of at least some of the reference hits while resolving a word of bits, the reference voltage signal provided by the bypass capacitor undergoes far less settling, remaining more stable and linear for a more accurate reference voltage. Furthermore, a smaller capacitor may be used for the bypass capacitor, reducing power consumption and area on chip.