Joe W Matthews

US Patent:

6697385, Feb 24, 2004

Filed:

Sep 23, 1997

Appl. No.:

08/935982

Inventors:

Joe P. Matthews - Savage MN

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H04J 306

US Classification:

370517, 370419, 370463, 370501, 375211

Abstract:

A circuit comprising a first circuit and a second circuit. The first circuit may be configured to present information after a delay in response to a plurality of transmit and receive inputs. The second circuit may be configured to adjust the amount of delay prior to presenting information. The second circuit may be implemented as a state machine.

US Patent:

6885714, Apr 26, 2005

Filed:

May 24, 2001

Appl. No.:

09/865208

Inventors:

Joe P. Matthews - Savage MN, US
Edward L. Grivna - Brooklyn Park MN, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H04L007/00

US Classification:

375354

Abstract:

An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a plurality of control signals and a select signal, in response to (i) a receive clock signal, (ii) a reference clock signal and (iii) a master clock signal. The second circuit may be configured to generate a read signal and a window signal in response to the plurality of control signals. The third circuit may be configured to generate a lock signal in response to (i) the reference clock signal, (ii) the select signal, (iii) the read signal and (iv) the window signal. The receive clock signal and the reference clock signal may be independent clocks configured to provide range control over one or more channels.

US Patent:

63112396, Oct 30, 2001

Filed:

Oct 29, 1998

Appl. No.:

9/182561

Inventors:

Joe P. Matthews - Savage MN

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H04Q 1104
H04J 316
G06F 738
G06F 300
G06F 1576

US Classification:

710 66

Abstract:

An architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media that may comprise a first circuit configured to present a first series of data packets having a first bit-width in response to a second series of data packets having a second bit-width and a second circuit configured to present a third series of data packets having said first bit-width in response to said second series of data packets. The first circuit may comprise a buffer circuit configured to hold one or more of the first series of data packets and a packer circuit configured to present the second series of data packets in response to the data packets held in the buffer circuit. The second circuit may comprise an unpacker circuit configured to present the third series of data packets and a buffer circuit configured to hold one or more of the third series of data packets.