Joel Edwin Jamias

Principal Engineer

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Location:

Mission Viejo, CA

Industry:

Semiconductors

Work:

Innophase
Principal Engineer
Intel Corporation
Engineering Consultant -- Digital Soc Subsystems Architect and Design Lead
Raytheon 2015 - 2018
Senior Principal Electrical Engineer
Qualcomm Irvine Sensors Pmc-Sierra Amd Teradyne Boeing 2008 - 2015
Engineering Consultant -- Asic and Soc Design
Blackberry Jul 2010 - Jun 2011
Senior Engineer

Education:

Stanford University
Cornell University
Bachelors, Bachelor of Science, Electrical Engineering University of California, Los Angeles
Master of Science, Masters, Electrical Engineering

Skills:

Asic
Soc
Vhdl
Verilog
Hardware Architecture
Ic
Low Power Design
High Speed Digital Design
Debugging
Technical Supervision and Management
Eda
Fpga
Embedded Systems
Static Timing Analysis
Functional Verification
Modelsim
Dft
Rtl To Gds2
Vlsi
Integrated Circuit Design
Tcl
Analog Circuit Design
Signal Integrity
Pcb Design
Circuit Design
Dsp
Nanoelectronics
Very Large Scale Integration

Interests:

Exploring New Cities
Stock
Dsp Design
Mixed Signal Simulation
Running
Other Interests
Quantum Devices
Karaoke Singing
Nanoelectronics
Hiking
Options Trading and Investing
Quantum Computing
Personal Finance
Church Activities
Low Power
Etf
Real Estate Investing
Yosemite
High Speed Digital

Joel Jamias Mission Viejo, CA

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Work:

TERADYNE
Tualatin, OR
Dec 2013 to Mar 2014
Consulting Engineer QUALCOMM
San Diego, CA
Jun 2012 to Aug 2013
Consulting Engineer IV AMD
Boxborough, MA
Jul 2011 to May 2012
Senior Staff Consulting Engineer RESEARCH IN MOTION
Scotts Valley, CA
Jul 2010 to Jun 2011
Senior ASIC Design Engineer PMC-SIERRA
Burnaby, BC
Dec 2009 to Mar 2010
Consulting Engineer IRVINE SENSORS
Costa Mesa, CA
Jul 2009 to Oct 2009
Consulting Engineer QUALCOMM
San Diego, CA
Aug 2008 to Feb 2009
Consulting Engineer INTEL, Santa Clara-Irvine-San Fran.-Sacto
Folsom, CA
Mar 1998 to Jan 2008
Senior ASIC Design Engineer TRW Space & Electronics
Redondo Beach, CA
May 1995 to Mar 1998
Senior Member of Technical Staff IBM
San Jose, CA
Oct 1987 to Feb 1995
Senior Associate Engineer

Education:

UNIVERSITY OF CALIFORNIA
Los Angeles, CA
Mar 2001
M.S. in Electrical Engineering CORNELL UNIVERSITY
Ithaca, NY
May 1987
B.S. in Electrical Engineering STANFORD UNIVERSITY
Stanford, CA
graduate courses in electrical engineering

Skills:

SKILLS: Deep-submicron ASIC / SoC design, encompassing micro-architecture, RTL logic design, synthesis, behavioral and gate-level simulation verification and debug, formal verification, static timing analysis, floorplanning, timing-driven layout supervision, DFT/DFx and BIST, burn-in and fault test generation, silicon test and debug, system integration and debug. Technical supervision. VHDL, Verilog, and ABEL logic design. RTL to GDS II development of ASIC IP blocks for a high-speed DDR3 PHY interface. Custom VLSI circuit design and layout. HSPICE and STARSIM circuit simulation. FPGA (Xilinx and Actel), PLD, and PCB design and debug. Signal integrity analysis and problem resolution. DSP, digital filter design, image processing, and speech processing. MATLAB and MACSYMA analysis. C, Fortran, and i960 assembly language programming. Tcl / Perl scripting. Scientific computing. EDA tools: Mentor (Modelsim / QuestaSim, Design Architect, DFT Advisor, FastScan ATPG), Synopsys (Design Compiler, DC Ultra, IC Compiler / ICC, DFT Compiler, PrimeTime, PTPX), ExtremeDA (GoldTime), Cadence (Opus, Composer, Virtuoso, Verilog-XL, Apollo APR, First Encounter, Encounter Conformal LEC formal verification), LogicVision ET (Embedded Test 4.1), Intel (CSE, Cougar, SALT, SHARK, BLAST), AMD (Tile Builder), and IBM (ASTAP, ETE, Aussim, LSSD RulesCheck, fault grading, Autogen). UNIX and Windows operating systems.