Joel J Mccormack from 819 Peakview Rd, Boulder, CO 80302, age 67, Phone: (303)4479162

Wikipedia

Joel McCormack

view source

Joel McCormack is the designer of the NCR Corporation version of the p-code machine which is a kind of Stack machine popular in the 1970s as the preferred ...

Resumes

Joel Mccormack

view source

Wikipedia References

Joel Mccormack

Work:

Area of science:

Computer scientist

Education:

Specialty:

Compiler

Area of science:

Architecture

Academic degree:

Professor • PHD

Professional scientist:

Compiler

Skills & Activities:

Activity:

Jogging

Skill:

Instruction • Software • Programming environment • Pascal

Us Patents

System And Method For Producing An Antialiased Image Using A Merge Buffer
view source
US Patent:

6633297, Oct 14, 2003
Filed:

Aug 20, 2001
Appl. No.:

09/934282
Inventors:

Joel James McCormack - Boulder CO
Keith Istvan Farkas - San Carlos CA
Norman P. Jouppi - Palo Alto CA
Larry Dean Seiler - Boylston MA
Robert Stephen McNamara - Portola Valley CA
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G06T 120
US Classification:

345506, 345419, 345421, 345423, 345629, 345582
Abstract:

In a graphics pipeline, a rasterizer circuit generates fragments for an image having multiple surfaces that have been tessellated into primitive objects, such as triangles. First and second fragments are associated with the same pixel. A merge buffer merges the first fragment with the second fragment when the two fragments belong to the same tessellated surface, the first fragments primitive is adjacent to the second fragments primitive, both fragments face either toward or away from the viewer, and the first and second fragment are sufficiently similar that merging is unlikely to introduce visually objectionable artifacts. A frame buffer receives fragments from the merge buffer, stores the fragments, combines the fragments into pixels, and outputs the pixels to a display.

Method And Apparatus For Tiled Polygon Traversal
view source
US Patent:

6714196, Mar 30, 2004
Filed:

Aug 20, 2001
Appl. No.:

09/934236
Inventors:

Joel James McCormack - Boulder CO
Robert Stephen McNamara - Portola Valley CA
Laura Edwards Mendyke - Calabasas CA
Todd Aldridge Dutton - Southborough MA
Assignee:

Hewlett-Packard Development Company L.P - Houston TX
International Classification:

G06T 1500
US Classification:

345423, 345419, 345614, 345622
Abstract:

A method and apparatus for visiting all stamps that are relevant to a two-dimensional convex polygonal object. The object is visited with a rectangular stamp, which contains one or more discrete sample points. A relevant location is one for which the object contains at least one of the stamps sample points when the stamp is placed at that location. Stamp locations are discrete points that are separated vertically by the stamps height, and horizontally by the stamps width. The stamp may move to a nearby position, or to a previously saved position, as it traverses the object. The plane in which the object lies is partitioned into rectangular tiles, which are at least as wide and high as the stamp. The invention visits stamp locations in an order that respects tile boundariesâthat is, it visits all locations within one tile before visiting any locations within another tile. The invention may also be used with further partitioning of the plane (metatiles), so that it will visit all locations within a metatile before visiting any locations within another metatile, and further visit all locations within a portion of a tile within the current metatile before visiting any locations within a portion of a different tile within the current metatile.

Efficient Movement Of Fragment Stamp
view source
US Patent:

7081903, Jul 25, 2006
Filed:

Dec 12, 2001
Appl. No.:

10/020729
Inventors:

Robert Stephen McNamara - Portola Valley CA, US
Joel James McCormack - Boulder CO, US
Laura Edwards Mendyke - Calabasas CA, US
Todd Aldridge Dutton - Southborough MA, US
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G09G 5/00
US Classification:

345614, 345423, 345441, 345469, 345613, 345622
Abstract:

A method and apparatus for visiting all productive stamp positions for a two-dimensional convex polygonal object. The object is visited with a stamp that has a stamp rectangle, and one or more discrete sample points. A productive location is one for which the object contains at least one of the stamp's sample points when the stamp is placed at that location. An unproductive location is one for which the object contains none of the stamp's sample points when the stamp is placed at that location. Stamp locations are discrete points that are separated vertically by the stamp rectangle's height, and horizontally by the stamp rectangle's width. The stamp may move to a nearby position, or to a previously saved position, as it traverses the object. The stamp moves in such a way as to visit all productive locations for an object while avoiding most of the unproductive locations.

Efficient Hardware A-Buffer Using Three-Dimensional Allocation Of Fragment Memory
view source
US Patent:

7336283, Feb 26, 2008
Filed:

Oct 24, 2002
Appl. No.:

10/280721
Inventors:

Joel James McCormack - Boulder CO, US
Norman P. Jouppi - Palo Alto CA, US
Larry Dean Seiler - Boylston MA, US
Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:

G06F 12/02
US Classification:

345543, 345544
Abstract:

A method and apparatus for arranging fragments in a graphics memory. Each pixel of a display has a corresponding list of fragments in the graphics memory. Each fragment describes a three-dimensional surface at a plurality of sample points associated with the pixel. A predetermined number of fragments are statically allocated to each pixel. Additional space for fragment data is dynamically allocated and deallocated. Each dynamically allocated unit of memory contains fragment data for a plurality of pixels. Fragment data are arranged to exploit modem DRAM capabilities by increasing locality of reference within a single DRAM page, by putting other fragments likely to be referenced soon in pages that belong to non-conflicting banks, and by maintaining bookkeeping structures that allow the relevant DRAM precharge and row activate operations to be scheduled far in advance of access to fragment data.

Reconfigurable High Performance Texture Pipeline With Advanced Filtering
view source
US Patent:

7649538, Jan 19, 2010
Filed:

Nov 3, 2006
Appl. No.:

11/556674
Inventors:

Alexander L. Minkin - Los Altos CA, US
Joel J. McCormack - Boulder CO, US
Paul S. Heckbert - Pittsburgh PA, US
Michael J. M. Toksvig - Palo Alto CA, US
Luke Y. Chang - San Mateo CA, US
Karim Abdalla - Menlo Park CA, US
Bo Hong - Fremont CA, US
John W. Berendsen - Beaconsfield, CA
Walter Donovan - Saratoga CA, US
Emmett M. Kilgariff - San Jose CA, US
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G06T 17/00
G06T 11/40
G09G 5/00
G09G 5/02
G06K 9/40
G06K 9/32
G06K 9/64
US Classification:

345582, 345428, 345587, 345606, 345552, 382254, 382260, 382300, 382303, 711100, 711113, 711123, 711127
Abstract:

Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Reconfigurable High-Performance Texture Pipeline With Advanced Filtering
view source
US Patent:

7884831, Feb 8, 2011
Filed:

Jan 19, 2010
Appl. No.:

12/689939
Inventors:

Alexander L. Minkin - Los Altos CA, US
Joel J. McCormack - Boulder CO, US
Paul S. Heckbert - Pittsburgh PA, US
Michael J. M. Toksvig - Palo Alto CA, US
Luke Y. Chang - San Mateo CA, US
Karim Abdalla - Menlo Park CA, US
Bo Hong - Fremont CA, US
John W. Berendsen - Beaconsfield, CA
Walter Donavan - Saratoga CA, US
Emmett M. Kilgariff - San Jose CA, US
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G06T 17/00
G06T 11/40
G09G 5/00
G09G 5/02
G06K 9/40
G06K 9/32
G06K 9/64
US Classification:

345582, 345428, 345587, 345606, 345552, 382254, 382260, 382300, 382303, 711100, 711113, 711123, 711127
Abstract:

Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Block Linear Memory Ordering Of Texture Data
view source
US Patent:

7916149, Mar 29, 2011
Filed:

Jan 4, 2005
Appl. No.:

11/029940
Inventors:

Walter E. Donovan - Saratoga CA, US
Emmett M. Kilgariff - San Jose CA, US
Karim M. Abdalla - Menlo Park CA, US
Joel J. McCormack - Boulder CO, US
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G06T 11/40
US Classification:

345552, 345530, 345543, 345544, 345564, 345582, 345587
Abstract:

A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e. g. , computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Block Linear Memory Ordering Of Texture Data
view source
US Patent:

8436868, May 7, 2013
Filed:

Mar 28, 2011
Appl. No.:

13/073020
Inventors:

Walter E. Donovan - Saratoga CA, US
Emmett M. Kilgariff - San Jose CA, US
Karim M. Abdalla - Menlo Park CA, US
Joel J. McCormack - Boulder CO, US
Assignee:

NVIDIA Corporation - Santa Clara CA
International Classification:

G09G 5/00
US Classification:

345587, 345543, 345544, 345582, 711170
Abstract:

A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size the mipmap level. A memory space (e. g. , computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.