John L Carson

US Patent:

6389404, May 14, 2002

Filed:

Dec 30, 1998

Appl. No.:

09/223476

Inventors:

John C. Carson - Corona Del Mar CA
Christ H. Saunders - Laguna Niguel CA

Assignee:

Irvine Sensors Corporation - Costa Mesa CA

International Classification:

G06F 1518

US Classification:

706 18, 709 20, 709 38

Abstract:

A neural processing module is disclosed which combines a weighted synapse array that performs âprimitive arithmeticâ (products and sums) in parallel with a weight change architecture and a data input architecture that collectively maximize the use of the weighted synapse array by providing it with signal permutations as frequently as possible. The neural processing module is used independently, or in combination with other modules in a planar or stacked arrangement.

US Patent:

6829237, Dec 7, 2004

Filed:

Oct 9, 2001

Appl. No.:

09/973857

Inventors:

John C. Carson - Corona Del Mar CA
Volkan H. Ozguz - Aliso Viejo CA

Assignee:

Irvine Sensors Corporation - Costa Mesa CA

International Classification:

H04L 1228

US Classification:

370386, 370388, 370389, 340 26, 257499, 257661, 257930

Abstract:

A compact multi-stage switching network ( ), and a router ( ) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports ( ) to selected ones of a second plurality of output ports ( ) comprising: a first stack ( ) of IC switching layers ( ) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit ( ); a second stack ( ) of IC switching layers ( ) that are stacked in physical contact with one another, each IC switching layer ( ) containing at least one switching element circuit ( ); and interconnecting circuitry ( ) that connects the first stack ( ) of IC layers to the second stack ( ) of IC layers to form the compact multi-stage switching network. The stacks ( ) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection. Also contemplated are the use of superconducting IC switching circuits ( ) and a suitable superconducting cooling housing ( ), as permitted by the compact nature of the multi-stage switching network ( ), in order to operate at high speed and low power.

US Patent:

7440449, Oct 21, 2008

Filed:

Oct 6, 2004

Appl. No.:

10/960712

Inventors:

John C. Carson - Corona Del Mar CA, US
Volkan H. Ozguz - Aliso Viejo CA, US

Assignee:

Irvine Sensors Corp. - Costa Mesa CA

International Classification:

H04L 12/28
H04L 12/56
H04L 29/00
H04L 39/00

US Classification:

370386, 370388, 370389, 257499, 257661, 257930, 340 26

Abstract:

A compact multi-stage switching network (), and a router () incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports () to selected ones of a second plurality of output ports () comprising: a first stack () of IC switching layers () that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (); a second stack () of IC switching layers () that are stacked in physical contact with one another, each IC switching layer () containing at least one switching element circuit (); and interconnecting circuitry () that connects the first stack () of IC layers to the second stack () of IC layers to form the compact multi-stage switching network. The stacks () are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection. Also contemplated are the use of superconducting IC switching circuits () and a suitable superconducting cooling housing (), as permitted by the compact nature of the multi-stage switching network (), in order to operate at high speed and low power.

US Patent:

8510244, Aug 13, 2013

Filed:

Mar 18, 2010

Appl. No.:

12/661537

Inventors:

John C. Carson - Corona del Mar CA, US
Volkan Ozguz - Aliso Viejo CA, US

Assignee:

ISC8 Inc. - Costa Mesa CA

International Classification:

G06E 1/00
G06E 3/00
G06F 15/18
G06G 7/00

US Classification:

706 27

Abstract:

An artificial synapse array and virtual neural space are disclosed. More specifically, a cognitive sensor system and method are disclosed comprising a massively parallel convolution processor capable of, for instance, situationally dependent identification of salient features in a scene of interest by emulating the cortical hierarchy found in the human retina and visual cortex.

US Patent:

20120092390, Apr 19, 2012

Filed:

Oct 13, 2011

Appl. No.:

13/272341

Inventors:

David Ludwig - Irvine CA, US
John Carson - Corona del Mar CA, US

International Classification:

G09G 5/10
H01L 33/00

US Classification:

345690, 257 84, 257E33001

Abstract:

A detector module which may comprise a black silicon detector for detecting incident radiation and generating a visible output to a display output pixel element such as one or more OLED elements. One or more vertically interconnected unit cells, which may be in the form of a plurality of vertically stacked and bonded layers, is disclosed having a detector layer comprising one or more black silicon detector elements, an amplification layer and a display layer having a dedicated display output pixel element. The layers are vertically interconnected by means of electrically conductive area interconnects such as electrically conductive through-silicon vias.

US Patent:

20120300048, Nov 29, 2012

Filed:

May 25, 2012

Appl. No.:

13/480629

Inventors:

John Carson - Corona del Mar CA, US

Assignee:

ISC8 Inc. - Costa Mesa CA

International Classification:

H04N 7/18

US Classification:

348 61, 348E07085

Abstract:

A device and method for the acquisition, processing and optimized transmission of video image data. The display output of an electronic viewing device is split by means of a beam-splitting element. A split portion of the image is detected by a detector and its output digitized. Regions of interest in the split image may be identified by eye-tracking or image saliency processing means to define salient regions in the split image. The salient regions in the split image are transmitted to a remote receiver at a higher resolution than the non-salient regions in the scene whereby video transmission bandwidth is reduced and optimized.

US Patent:

20130044317, Feb 21, 2013

Filed:

Aug 1, 2012

Appl. No.:

13/563794

Inventors:

James Justice - Newport Beach CA, US
John Carson - Corona del Mar CA, US
Medhat Azzazy - Laguna Niguel CA, US
Ying Hsu - San Clemente CA, US

Assignee:

ISC8 Inc. - Costa Mesa CA

International Classification:

G01J 3/45

US Classification:

356300, 356456

Abstract:

A sensor suite comprising a LIDAR transmitter and receiver element and a visible imager element. The transmitter operates with a plurality of selectable beam-forming optics or a tilt-tip element. A Risley or counter-rotating prism set element permits beam-steering with lower size, weight and power (SWaP). The optics for the system may be configured in a Cassegrain-type configuration in cooperation with a plurality of beam-splitting elements to permit predetermined spectrums of the received electromagnetic spectrum to be provided respectively to the LIDAR receiver and the visible imager. One or a plurality of laser illuminator analysis spectrometers are provided for the detection of incoming laser illumination from an external source which may be in the form of a micro-lamellar spectrometer element.

US Patent:

46461280, Feb 24, 1987

Filed:

Apr 8, 1985

Appl. No.:

6/720902

Inventors:

John C. Carson - Corona del Mar CA
Stewart A. Clark - Irvine CA

Assignee:

Irvine Sensors Corporation - Costa Mesa CA

International Classification:

H01L 2348

US Classification:

357 74

Abstract:

A high-density electronic package module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of thin film circuitry on the access ends, each access plane is etched to cut back the semiconductor material then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.