John S Clapp

US Patent:

6433714, Aug 13, 2002

Filed:

Dec 20, 2000

Appl. No.:

09/746724

Inventors:

John S. Clapp - Wyomissing PA
Glen A. Johnson - Reading PA
Douglas Baird Lebo - Birdsboro PA
Lawrence Peter Swanson - Fleetwood PA

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H03M 110

US Classification:

341121, 341144

Abstract:

The present invention provides methods and apparatus for trimming semiconductor devices and circuits, such as pin electronics circuits used in automated test equipment (ATE) systems and the like, without requiring a laser trimming operation. In a preferred embodiment, the present invention addresses the need to precisely adjust a reference current and/or voltage by replacing a conventional current/voltage reference source with a digital-to-analog (D/A) converter. A select switch or mechanism is preferably coupled to the input of the D/A converter and operatively presents a digital input word to the D/A converter by selectively reading the digital word from at least one of a data register and a fuse register. The data register is preferably used during testing of the overall current or voltage reference by iteratively trying various digital input codes while concurrently measuring the analog output signal from the D/A converter until the output signal sufficiently matches a predetermined output value. The fuse register, which comprises a plurality of fusible links, is then preferably blown to permanently store the input code word that provides the desired reference output.

US Patent:

20020080538, Jun 27, 2002

Filed:

Dec 27, 2000

Appl. No.:

09/747924

Inventors:

John Clapp - Wyomissing PA, US
Thanh Nguyen - Temple PA, US

International Classification:

H02H009/00

US Classification:

361/058000, 361/093900

Abstract:

A current limiter circuit for limiting current in an electrical circuit element such as the magneto-resistive portion of a read head forming a portion of a hard disk drive and including: a first circuit connected to one end of the circuit element for applying a bias current of a desired value to the circuit element in response to the value to an input signal; a second circuit connected to the other end of the circuit element for setting the amplitude of the voltage signal generated across the circuit element in response to the bias current; and a third electrical circuit connected to both the first and second circuits for limiting the value of bias current to a predetermined level for an abnormal event such as a current surge, a short circuit, or any other type of undesired current operating condition.

US Patent:

55393349, Jul 23, 1996

Filed:

Dec 16, 1992

Appl. No.:

7/991622

Inventors:

John S. Clapp - Plano TX
Wayne T. Chen - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 190185
H03K 19003

US Classification:

326 68

Abstract:

A voltage level shifter circuit (10) for outputting an output high (18) and output low (18) signal is provided which accommodates multiple power supplies (12 and 22) at different relative voltage to each other. The voltage level shifter (10) includes an input stage (24) which is characterized by voltage ranges applicable to the process used to make the circuit. The voltage level shifter circuit includes an output stage (18) which is also characterized by the same voltage ranges which cannot be exceeded. The output stage outputs the translated output high (16) and output low (18) voltage signals. A clamping network (20) is employed to ensure that the output stage voltage ranges are not exceeded. The present invention implements a high voltage level shifter (10) using low voltage components by extending the breakdown capability of the voltage level shifter circuit (10) past the breakdown voltage of any single component in the circuit.

US Patent:

54670500, Nov 14, 1995

Filed:

Jan 4, 1994

Appl. No.:

8/177811

Inventors:

John S. Clapp - Reinholds PA
Wayne T. Chen - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 110
H03K 508
H03K 19084

US Classification:

327530

Abstract:

A dynamic biasing circuit is disclosed that includes a blocking current source (20) having a first current path connected to a first node (NODE 1) and a second current path connected to a second node (NODE 3). A linear source follower (22) has a first current path connected to the second node (NODE 3), a second current path connected to a voltage reference (24), and an input connected to the first node (NODE 1). A parasitic capacitor (26) is connected to the first node (NODE 1) and to ground potential, and a parasitic capacitor (28) is connected to the second node (NODE 3) and to ground potential.

US Patent:

54125316, May 2, 1995

Filed:

Jan 5, 1993

Appl. No.:

8/000843

Inventors:

John S. Clapp - Plano TX

Assignee:

Texas Instruments Incorporated - Ballas TX

International Classification:

H01H 4700

US Classification:

361190

Abstract:

A circuit (16) having an extended breakdown capability is provided for switching an inductive load driver (12). The circuit (16) includes a first switch (18) for providing a first drive voltage when the first switch (18) is closed. A second switch (20) is provided for receiving the first drive voltage from the first switch (18) and delivering the first drive voltage to the inductive load driver (12) when the second switch (20) is closed. The second switch (20) limits the voltage across the first switch (18) to a predetermined level when the first switch (18) is open. A third switch (22) provides a second drive voltage to the inductive load driver (12) when the third switch (22) is closed.