John Howard Conley

US Patent:

20040164362, Aug 26, 2004

Filed:

Feb 23, 2004

Appl. No.:

10/784662

Inventors:

John Conley - Camas WA, US
Yoshi Ono - Camas WA, US
Wei Gao - Vancouver WA, US

International Classification:

H01L029/76

US Classification:

257/407000

Abstract:

A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel region; forming a first metal barrier overlying the gate insulator, having a thickness of less than 5 nanometers (nm); forming a second metal gate electrode overlying the first metal barrier, having a thickness of greater than 10 nm; and, establishing a gate electrode work function exclusively responsive to the second metal. The second metal gate electrode can be one of the following materials: elementary metals such as p+ poly, n+ poly. Ta, W, Re, RuO2, Pt, Ti, Hf, Zr, Cu, V, Ir, Ni, Mn, Co, NbO, Pd, Mo, TaSiN, and Nb, and binary metals such as WN, TaN, and TiN. The first metal barrier can be a binary metal, such as TaN, TiN, or WN.

US Patent:

20040168627, Sep 2, 2004

Filed:

Feb 27, 2003

Appl. No.:

10/376774

Inventors:

John Conley - Camas WA, US
Yoshi Ono - Camas WA, US
Rajendra Solanki - Portland OR, US

Assignee:

Sharp Laboratories of America, Inc.

International Classification:

C30B023/00
C30B025/00
C30B028/12
C30B028/14

US Classification:

117/089000

Abstract:

An atomic layer deposition method to deposit a oxide thin film is provided. The method employs a nitrate ligand in a first hafnium precursor as an oxidizer for a second hafnium precursor to form the hafnium oxide. Using a hafnium nitrate precursor and a hafnium chloride precursor, the method is well suited for the deposition of a high k hafnium oxide dielectric for gate dielectric or capacitor dielectric applications on a hydrogen-terminated silicon surface.

US Patent:

20040171222, Sep 2, 2004

Filed:

Feb 27, 2003

Appl. No.:

10/376795

Inventors:

Wei Gao - Vancouver WA, US
John Conley - Camas WA, US
Yoshi Ono - Camas WA, US

Assignee:

Sharp Laboratories of America Inc.

International Classification:

H01L021/336

US Classification:

438/283000, 257/401000

Abstract:

A dual-gate MOSFET with metal gates and a method for setting threshold voltage in such a MOSFET is provided. The method comprises: forming a gate oxide layer overlying first and second channel regions; forming a first metal layer having a first thickness overlying the gate oxide layer; forming a second metal layer having a second thickness overlying the first metal layer first thickness; selectively removing the second metal layer overlying the first channel region; forming a third metal layer; establishing a first MOSFET with a gate work function responsive to the thicknesses of the first and third metal layer overlying the first channel region; and, establishing a second MOSFET, complementary to the first MOSFET, with a gate work function responsive to the combination of the thicknesses of the first, second, and third metal layers overlying the second channel region.

US Patent:

20040171280, Sep 2, 2004

Filed:

Feb 27, 2003

Appl. No.:

10/376794

Inventors:

John Conley - Camas WA, US
Yoshi Ono - Camas WA, US
Rajendra Solanki - Portland OR, US

Assignee:

Sharp Laboratories of America, Inc.

International Classification:

H01L021/336
H01L021/31
H01L021/469

US Classification:

438/785000, 438/287000

Abstract:

An atomic layer deposition method to deposit an oxide nanolaminate thin film is provided. The method employs a nitrate ligand in a first precursor as an oxidizer for a second precursor to form the oxide nanolaminates. Using a hafnium nitrate precursor and an aluminum precursor, the method is well suited for the deposition of a high k hafnium oxide/aluminum oxide nanolaminate dielectric for gate dielectric or capacitor dielectric applications on a hydrogen-terminated silicon surface.

US Patent:

20040203254, Oct 14, 2004

Filed:

Apr 11, 2003

Appl. No.:

10/412550

Inventors:

John Conley - Camas WA, US
Yoshi Ono - Camas WA, US
Gregory Stecker - Vancouver WA, US

Assignee:

Sharp Laboratories of America, Inc.

International Classification:

H01L021/31
H01L021/469

US Classification:

438/778000, 438/782000

Abstract:

A method of forming a layer of high-k dielectric material in an integrated circuit includes preparing a silicon substrate; forming a high-k dielectric layer by a sequence of ALD cycles including: depositing a first layer of metal ligand using ALD with an oxygen-containing first precursor; and depositing a second layer of metal ligand using ALD with a second precursor; repeating the sequence of ALD cycles N times until a near-critical thickness of metal oxide is formed; annealing the substrate and metal oxide layers every N ALD cycles in an elevated temperature anneal; repeating the sequence of ALD cycles and elevated temperature anneals until a high-k dielectric layer of desired thickness is formed; annealing the substrate and the metal oxide layers in a final annealing step; and completing the integrated circuit.

US Patent:

20050070079, Mar 31, 2005

Filed:

Sep 30, 2003

Appl. No.:

10/677035

Inventors:

John Conley - Camas WA, US
Yoshi Ono - Camas WA, US

International Classification:

H01L021/3205

US Classification:

438585000

Abstract:

Methods of forming an interfacial layer on a hydrogen-passivated substrate are provided. These methods utilize atomic layer deposition techniques incorporating metal nitrate-based precursors, such as hafnium nitrate or zirconium nitrate, without introducing a hydrating agent, or oxidizing agent, such as water, during the formation of the interfacial layer. Also provided are methods of forming high-k films, by first forming an interfacial layer on the surface of a hydrogen-passivated substrate, and then depositing one, or more, high-k dielectric films.

US Patent:

20050170667, Aug 4, 2005

Filed:

Mar 24, 2005

Appl. No.:

11/089947

Inventors:

John Conley - Camas WA, US
Yoshi Ono - Camas WA, US
Rajendra Solanki - Portland OR, US

International Classification:

H01L021/8242
H01L021/336
B05D005/12

US Classification:

438785000, 438287000, 438240000, 427126400, 427126300

Abstract:

An atomic layer deposition method to deposit an oxide nanolaminate thin film is provided. The method employs a nitrate ligand in a first precursor as an oxidizer for a second precursor to form the oxide nanolaminates. Using a hafnium nitrate precursor and an aluminum precursor, the method is well suited for the deposition of a high k hafnium oxide/aluminum oxide nanolaminate dielectric for gate dielectric or capacitor dielectric applications on a hydrogen-terminated silicon surface.

US Patent:

20050205969, Sep 22, 2005

Filed:

Mar 19, 2004

Appl. No.:

10/805158

Inventors:

Yoshi Ono - Camas WA, US
John Conley - Camas WA, US
Pooran Joshi - Vancouver WA, US

International Classification:

H01L023/58
H01L021/336

US Classification:

257645000, 257651000, 438288000

Abstract:

The present invention discloses a non-volatile memory cell structure utilizing a charge trapping high-k dielectric in the place of the triple film stack (tunnel dielectric layer/charge trapping layer/blocking layer). The charge trapping characteristic of the high-k dielectric can be further improved by exposing the high-k dielectric layer to an treatment process such as a plasma exposure using excited state oxygen (e.g. oxygen plasma) ambient. By using a single layer as the charge trapping gate dielectric, the present invention presents a simple and inexpensive solution that permits device scaling to very small dimensions, together with the ease of device fabrication processes. The present invention also discloses the fabrication process for the charge trapping high-k gate dielectric non-volatile memory cell structure, applicable to bulk device, TFT device or SOI device.