John B Conrad

US Patent:

7299370, Nov 20, 2007

Filed:

Jun 10, 2003

Appl. No.:

10/459011

Inventors:

Varghese George - Folsom CA, US
Mark A. Newman - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Inder M. Sodhi - Folsom CA, US
Tanjeer R. Khondker - Folsom CA, US
Mathew B. Nazareth - El Dorado Hills CA, US
John B. Conrad - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 23/02

US Classification:

713322, 713300, 713310, 713320, 713321, 713323, 713324, 713330, 713340

Abstract:

A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.

US Patent:

7664970, Feb 16, 2010

Filed:

Dec 30, 2005

Appl. No.:

11/323254

Inventors:

Sanjeev Jahagirdar - Folsom CA, US
George Varghese - Folsom CA, US
John B. Conrad - Folsom CA, US
Robert Milstrey - Citrus Heights CA, US
Stephen A. Fischer - Gold River CA, US
Alon Navch - Ramat Hasharon, IL
Shai Rotem - Haifa, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/00
G06F 1/26
G06F 15/00
G06F 11/00

US Classification:

713300, 713320, 713324, 712 28, 714 15

Abstract:

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

US Patent:

20130013945, Jan 10, 2013

Filed:

Sep 14, 2012

Appl. No.:

13/619998

Inventors:

Sanjeev Jahagirdar - Folsom CA, US
Varghese George - Folsom CA, US
John B. Conrad - Folsom CA, US
Robert Milstrey - Citrus Heights CA, US
Stephen A. Fischer - Gold River CA, US
Alon Naveh - Ramat Hasharon, IL
Shai Rotem - Haifa, IL

International Classification:

G06F 1/32

US Classification:

713320

Abstract:

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

US Patent:

20170269672, Sep 21, 2017

Filed:

Dec 11, 2015

Appl. No.:

14/966708

Inventors:

- Santa Clara CA, US
Varghese George - Folsom CA, US
John B. Conrad - Folsom CA, US
Robert Milstrey - Citrus Heights CA, US
Stephen A. Fischer - Gold River CA, US
Alon Naveh - Ramat Hasharon, IL
Shai Rotem - Haifa, IL

International Classification:

G06F 1/32
G06F 12/08

Abstract:

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

US Patent:

20170017297, Jan 19, 2017

Filed:

Sep 29, 2016

Appl. No.:

15/280057

Inventors:

- Santa Clara CA, US
Varghese George - Folsom CA, US
John B. Conrad - Folsom CA, US
Robert Milstrey - Citrus Heights CA, US
Stephen A. Fischer - Gold River CA, US
Alon Naveh - Ramat Hasharon, IL
Shai Rotem - Haifa, IL

International Classification:

G06F 1/32
G06F 9/44

Abstract:

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

US Patent:

20160091958, Mar 31, 2016

Filed:

Dec 4, 2015

Appl. No.:

14/959549

Inventors:

- Santa Clara CA, US
Varghese George - Folsom CA, US
John Conrad - Folsom CA, US
Robert Milstrey - Citrus Heights CA, US
Stephen A. Fischer - Gold River CA, US
Alon Naveh - Ramat Hasharon, IL
Shai Rotem - Haifa, IL

International Classification:

G06F 1/32

Abstract:

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

US Patent:

20150169043, Jun 18, 2015

Filed:

Feb 25, 2015

Appl. No.:

14/630909

Inventors:

- Santa Clara CA, US
Varghese George - Folsom CA, US
John Conrad - Folsom CA, US
Robert Milstrey - Citrus Heights CA, US
Stephen A. Fischer - Gold River CA, US
Alon Naveh - Ramat Hasharon, IL
Shai Rotem - Haifa, IL

International Classification:

G06F 1/32

Abstract:

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

US Patent:

20150058667, Feb 26, 2015

Filed:

Sep 25, 2014

Appl. No.:

14/496345

Inventors:

- Santa Clara CA, US
Varghese George - Folsom CA, US
John B. Conrad - Folsom CA, US
Robert Milstrey - Citrus Heights CA, US
Stephen A. Fischer - Gold River CA, US
Alon Naveh - Ramat Hasharon, IL
Shai Rotem - Haifa, IL

International Classification:

G06F 1/32
G11C 7/10
G06F 12/08
G06F 11/14

US Classification:

714 10, 713323, 711125, 711105, 711130

Abstract:

Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.