John J Conway

US Patent:

45218480, Jun 4, 1985

Filed:

Aug 27, 1981

Appl. No.:

6/296931

Inventors:

Kenneth E. Bruce - Nashua NH
Ralph M. Lombardo - Lowell MA
Bruce H. Tarbox - Billerica MA
John W. Conway - Waltham MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 304
G06F 946

US Classification:

364200

Abstract:

An error detection system is disclosed for not only indicating but eliminating certain errors which may occur during the transfer of information between communication busses in a data processing system wherein plural communication busses each provide a common information path to plural data processing units including memory units, peripheral control units, central processing units and ISL units, and wherein each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs. The error detection system requires no special supporting software or firmware on the part of any data processing unit on any of the communication busses.

US Patent:

40004856, Dec 28, 1976

Filed:

Jun 30, 1975

Appl. No.:

5/591904

Inventors:

George J. Barlow - Tewksbury MA
Frank V. Cassarino - Weston MA
John W. Conway - Waltham MA
David B. O'Keefe - Tyngsboro MA

Assignee:

Honeywell Information Systems, Inc. - Waltham MA

International Classification:

G06F 918

US Classification:

3401725

Abstract:

A central processing system which includes a plurality of units coupled over a common electrical bus for the transfer of information between any two units, includes one unit in which there is a shareable resource such as a memory for example. Apparatus is provided for any units to share such resource. Further apparatus is provided for enabling any of such units so sharing the resource to lock out any other unit which presents a specified control signal to the unit incorporating the resource.

US Patent:

42349192, Nov 18, 1980

Filed:

Oct 31, 1978

Appl. No.:

5/956385

Inventors:

Kenneth E. Bruce - Nashua NH
George J. Barlow - Tewksbury MA
John W. Conway - Waltham MA
Ralph M. Lombardo - Lowell MA
John J. Bradley - Framingham MA
David B. O'Keefe - Westford MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 304

US Classification:

364200

Abstract:

A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.

US Patent:

44333765, Feb 21, 1984

Filed:

Dec 15, 1980

Appl. No.:

6/216600

Inventors:

Ralph M. Lombardo - Lowell MA
John J. Bradley - Framingham MA
Kenneth E. Bruce - Nashua NH
John W. Conway - Waltham MA
David B. O'Keefe - Westford MA
Bruce H. Tarbox - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 304

US Classification:

364200

Abstract:

A logic system is provided for accommodating the exchange of information between two or more communication busses of a data processing system, wherein plural central processing units and plural memory units on independent communication busses may have same logic addresses. Memory and CPU addresses are translated at the bus rate through a multiplicity of flexible address translation ranges to enable a data processing unit on one communication bus to access an apparent contiguous range of addresses encompassing all data processing units on all communication busses.

US Patent:

39939812, Nov 23, 1976

Filed:

Jun 30, 1975

Appl. No.:

5/591964

Inventors:

Frank V. Cassarino - Weston MA
George J. Barlow - Tewksbury MA
George J. Bekampis - Sudbury MA
John W. Conway - Waltham MA
Richard A. Lemay - Bolton MA
David B. O'Keefe - Tyngsboro MA
Douglas L. Riikonen - Westford MA
William E. Woods - Natwick MA

Assignee:

Honeywell Information Systems, Inc. - Waltham MA

International Classification:

G06F 304
G06F 1300

US Classification:

3401725

Abstract:

In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus during asynchronously generated information bus transfer cycles, the units are coupled in a priority network and depending upon their respective priority may gain access to the bus before a lower priority unit is so enabled. Each one of the units includes apparatus for responding to a request for the transfer of information from another unit by providing any one of up to three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for a relatively extended period of time and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.

US Patent:

42362091, Nov 25, 1980

Filed:

Oct 31, 1978

Appl. No.:

5/956389

Inventors:

Ralph M. Lombardo - Lowell MA
George J. Barlow - Tewksbury MA
John J. Bradley - Framingham MA
Kenneth E. Bruce - Nashua NH
John W. Conway - Waltham MA
Bruce H. Tarbox - Billerica MA

Assignee:

Honeywell Information Systems Inc. - Waltham MA

International Classification:

G06F 304
G06F 1300

US Classification:

364200

Abstract:

A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.

US Patent:

42310865, Oct 28, 1980

Filed:

Oct 31, 1978

Appl. No.:

5/956382

Inventors:

Bruce H. Tarbox - Billerica MA
Kenneth E. Bruce - Nashua NH
John W. Conway - Waltham MA
Ralph M. Lombardo - Lowell MA

Assignee:

Honeywell Information Systems, Inc. - Waltham MA

International Classification:

G06F 946
G06F 304

US Classification:

364200

Abstract:

A logic system in an intersystem link (ISL) unit is provided for avoiding deadlock conditions which may occur in a data processing system wherein multiple CPUs on one communication bus attempt to communicate with resources on remote communication busses. The data processing system has plural communication busses, each providing a common information path to plural data processing units including memory units, peripheral control units, central processing units (CPUs) and ISL units, and each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs.

US Patent:

48316202, May 16, 1989

Filed:

Jun 13, 1988

Appl. No.:

7/207891

Inventors:

John W. Conway - Waltham MA
Robert J. Farrell - Wakefield MA
Allen C. Hirtle - Littleton MA
Leonard E. Niessen - Framingham MA

Assignee:

Bull HN Information Systems Inc. - Billerica MA

International Classification:

H04J 300

US Classification:

370 85

Abstract:

A local area network (LAN) system is provided that is capable of accommodating a variety of computer subsystem types, and having a LAN controller which can control at substantially the same time a plurality of LANs of the same type or a plurality of different types of LANs.