John D Eng

US Patent:

46112022, Sep 9, 1986

Filed:

Oct 18, 1983

Appl. No.:

6/543108

Inventors:

Robert S. DiNitto - Chelsea MA
Thomas C. Porcher - Stow MA
John W. Eng - Southborough MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G09G 106

US Classification:

340724

Abstract:

The present invention is employed in a system which has a bit map memory connected to a CRT display device and the CRT display device can display a fixed region of information and a scrollable region of information. In a preferred embodiment, the system uses a graphic display control circuit to change starting addresses and length ending values of the fixed and scrollable regions in the bit map memory. By changing the starting address one scan line per frame, without any actual transfer of data in memory, from one location to another location, the present system effects a "smooth" scroll. The system is able to scroll upward and downward. The system uses logic circuitry to load an off screen segment of the bit map memory with additional scrollable information, so that (in an upward scroll load) as a top line of the scrollable information region is no longer displayed, new information will be displayed at the bottom line of said scrollable region. On the other hand during a downward scroll, a bottom line of information on the scrollable region of the screen will fade out and new information is added, from the off screen region, of the bit map memory to provide information for a new top line. In addition the system has the ability to reorganize the information in the bit map memory in the event the size or location of the fixed region is to be altered.

US Patent:

46252037, Nov 25, 1986

Filed:

Oct 18, 1983

Appl. No.:

6/543107

Inventors:

Robert S. DiNitto - Chelsea MA
Thomas C. Porcher - Stow MA
John W. Eng - Southborough MA
Charles S. Namias - Burlington MA
David B. Hughes - Hudson MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G09G 114

US Classification:

340750

Abstract:

The present invention includes a microprocessor which acts to generate groups of its signals from its read only memory (ROM) thereby forming character representations of groups of coded signals, such as ASCII coded signals, coming from a main data processing device. The groups of bit signals are temporarily stored in a buffer which at a subsequent time transmits, in parallel, groups of said bit signals to a bit map memory through some logic circuitry. The group, or block, transfer of said bit signals in parallel, occurs during horizontal or vertical blank periods. The parallel transfer during the blank periods provides part of the basis for acceleration of the data to a display device as compared with the prior art. In addition, the microprocessor provides address information signals to a graphic display controller, which in turn provides starting addresses, for the locations of the bit signals. In addition a bit map memory device is employed to provide pixel information to a CRT display device to create the characters which are to be shown.