John Greg Halbert

US Patent:

6785190, Aug 31, 2004

Filed:

May 20, 2003

Appl. No.:

10/442335

Inventors:

Kuljit S. Bains - Olympia WA
John Halbert - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 800

US Classification:

365235, 36523003

Abstract:

An efficient invention for opening two pages of memory for a DRAM are discussed.

US Patent:

6954822, Oct 11, 2005

Filed:

Aug 2, 2002

Appl. No.:

10/211680

Inventors:

Kuljit S. Bains - Olympia WA, US
Herbert Hum - Portland OR, US
John Halbert - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711 5, 711 3, 711128, 36523002, 36523003, 365239

Abstract:

Methods and apparatuses for mapping cache contents to memory arrays. In one embodiment, an apparatus includes a processor portion and a cache controller that maps the cache ways to memory banks. In one embodiment, each bank includes data from one cache way. In another embodiment, each bank includes data from each way. In another embodiment, memory array banks contain data corresponding to sequential cache lines.

US Patent:

6996749, Feb 7, 2006

Filed:

Nov 13, 2003

Appl. No.:

10/713564

Inventors:

Kuljit S. Bains - Olympia WA, US
Robert M. Ellis - Hillsboro OR, US
Chris B. Freeman - Portland OR, US
John B. Halbert - Beaverton OR, US
David Zimmerman - El Dorado Hills CA, US

Assignee:

Intel Coporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 42, 714742

Abstract:

Some embodiments of the invention enable debugging functionality for memory devices residing on a memory module that are buffered from the memory bus by a buffer chip. Some embodiments map connector signals from a tester coupled to the high speed interface between the buffer chip and the memory bus to an interface between the buffer chip and the memory devices. During test mode, some embodiments bypass the normal operational circuitry of the buffer chip and provide a direct connection to the memory devices. Other embodiments use the existing architecture of the buffer chip to convert high speed pins into low speed pins and map them to pins that are connected to the memory devices. Other embodiments are described in the claims.

US Patent:

7054999, May 30, 2006

Filed:

Aug 2, 2002

Appl. No.:

10/210908

Inventors:

Kuljit S. Bains - Olympia WA, US
Herbert Hum - Portland OR, US
John Halbert - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711128, 711105, 711145, 711167, 36523002, 36523003

Abstract:

A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

US Patent:

7281079, Oct 9, 2007

Filed:

Dec 31, 2003

Appl. No.:

10/750154

Inventors:

Kuljit S. Bains - Olympia WA, US
John B. Halbert - Beaverton OR, US
Randy B. Osborne - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711 5, 711154

Abstract:

Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.

US Patent:

7349233, Mar 25, 2008

Filed:

Mar 24, 2006

Appl. No.:

11/388464

Inventors:

Kuljit S. Bains - Olympia WA, US
John Halbert - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 5/06
G11C 5/02
G11C 7/10

US Classification:

365 63, 365 51, 36518902, 36523003

Abstract:

In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the groups of memory banks. The chip also includes circuitry to perform a read operation by providing read data from at least one of the banks of each of the groups of memory banks to its corresponding group of output conductors. Other embodiments are described.

US Patent:

7350016, Mar 25, 2008

Filed:

Jan 10, 2006

Appl. No.:

11/329994

Inventors:

Kuljit S. Bains - Olympia WA, US
Herbert Hum - Portland OR, US
John Halbert - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711 3, 711128, 711202, 711211, 365 49, 36523001, 36523002, 36523003

Abstract:

A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

US Patent:

7404055, Jul 22, 2008

Filed:

Mar 28, 2006

Appl. No.:

11/392471

Inventors:

Kuljit Bains - Olympia WA, US
John Halbert - Beaverton OR, US
Greg Lemos - Folsom CA, US
Randy Osborne - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711165, 711209, 711212, 711217

Abstract:

In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.