John Thomas Halbert

US Patent:

6449213, Sep 10, 2002

Filed:

Sep 18, 2000

Appl. No.:

09/664192

Inventors:

James M. Dodd - Shingle Springs CA
Michael W. Williams - Citrus Heights CA
John B. Halbert - Beaverton OR
Randy M. Bonella - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 800

US Classification:

365233, 365193

Abstract:

A memory interface scheme reduces propagation delay by utilizing source-synchronous signaling to transmit address/command information to memory devices. A memory module in accordance with the present invention may include an address/command buffer that samples address/command information responsive to an address/command strobe signal and then passes the address/command information to a memory device on the module. A retiming circuit may be used to control the timing of read-return data from a memory device on the module.

US Patent:

6530006, Mar 4, 2003

Filed:

Sep 18, 2000

Appl. No.:

09/664982

Inventors:

James M. Dodd - Shingle Springs CA
Michael W. Williams - Citru Heights CA
John Halbert - Beaverton OR
Randy M. Bonella - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711167, 711105, 710 52

Abstract:

The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.

US Patent:

6553450, Apr 22, 2003

Filed:

Sep 18, 2000

Appl. No.:

09/664985

Inventors:

Jim M. Dodd - Shingle Springs CA
Michael W. Williams - Citrus Heights CA
John B. Halbert - Beaverton OR
Randy M. Bonella - Portland OR
Chung Lam - Redwood City CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1202

US Classification:

711105, 711157, 711168, 710 52

Abstract:

Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

US Patent:

6766385, Jul 20, 2004

Filed:

Jan 7, 2002

Appl. No.:

10/041679

Inventors:

James M. Dodd - Shingle Springs CA
Brian P. Johnson - Folsom CA
Jay C. Wells - Folsom CA
John B. Halbert - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1328

US Classification:

710 35, 710 10, 710 33, 711 5, 711105, 711154, 711169, 711170, 711171, 711172, 712 1, 712210, 712220, 712225

Abstract:

The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

US Patent:

6952745, Oct 4, 2005

Filed:

Jun 25, 2004

Appl. No.:

10/877387

Inventors:

James M. Dodd - Shingle Springs CA, US
Brian P. Johnson - Folsom CA, US
Jay C. Wells - Folsom CA, US
John B. Halbert - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F013/28
G06F013/00
G06F013/14
G06F003/00
G06F012/00

US Classification:

710 35, 710 10, 710 33, 711 5, 711105, 711154, 711169, 711170, 711171, 711172, 712 1, 712210, 712220, 712225

Abstract:

The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

US Patent:

7523230, Apr 21, 2009

Filed:

May 24, 2005

Appl. No.:

11/137314

Inventors:

James M. Dodd - Shingle Springs CA, US
Brian P. Johnson - Folsom CA, US
Jay C. Wells - Folsom CA, US
John B. Halbert - Beaverton OR, US

International Classification:

G06F 13/28
G06F 13/00
G06F 13/14
G06F 3/00
G06F 12/00

US Classification:

710 35, 710 10, 710 33, 711 5, 711105, 711154, 711169, 711170, 711171, 711172, 712 1, 712210, 712220, 712225

Abstract:

The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.