John Allen Halbert

US Patent:

20180024878, Jan 25, 2018

Filed:

Oct 3, 2017

Appl. No.:

15/724222

Inventors:

- Santa Clara CA, US
Bill NALE - Livermore CA, US
Kuljit S. BAINS - Olympia WA, US
John B. HALBERT - Beaverton OR, US

International Classification:

G06F 11/10
G06F 11/00

Abstract:

Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

US Patent:

20160283318, Sep 29, 2016

Filed:

Mar 27, 2015

Appl. No.:

14/670413

Inventors:

- Santa Clara CA, US
Bill Nale - Livermore CA, US
Kuljit S. Bains - Olympia WA, US
John B. Halbert - Beaverton OR, US

International Classification:

G06F 11/10
G06F 3/06

Abstract:

Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.