John G Halbert

US Patent:

20130272049, Oct 17, 2013

Filed:

Dec 2, 2011

Appl. No.:

13/997148

Inventors:

Pete Vogt - Boulder CO, US
Andre Schaefer - Braunschweig, DE
Warren Morrow - Steilacoom WA, US
John Halbert - Beaverton OR, US
Jin Kim - Beaverton OR, US
Kenneth Shoemaker - Los Altos Hills CA, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

G11C 5/06
H01L 23/48

US Classification:

365 63, 257774

Abstract:

Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.