John Brandon Halbert

Address:

8216 NE 63 St, Vancouver, WA 98662

Phone:

(360)2541285

VIN:

4T1BE46K79U292418

Make:

TOYOTA

Model:

CAMRY

Year:

2009

US Patent:

6369605, Apr 9, 2002

Filed:

Sep 18, 2000

Appl. No.:

09/664994

Inventors:

Randy Bonella - Portland OR
John Halbert - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 1716

US Classification:

326 30, 326 86, 326 90

Abstract:

An output driver circuit within an electronic device to provide a configurable driver circuit. When placed in a first mode of operation, the driver circuit drives an output signal. When placed in a second mode of operation, the driver circuit provides impedance matching to prevent signal reflection.

US Patent:

6487102, Nov 26, 2002

Filed:

Sep 18, 2000

Appl. No.:

09/666528

Inventors:

John B. Halbert - Beaverton OR
Randy M. Bonella - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 502

US Classification:

365 51, 365 52, 365 63

Abstract:

The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.

US Patent:

6493250, Dec 10, 2002

Filed:

Dec 28, 2000

Appl. No.:

09/753024

Inventors:

John B. Halbert - Beaverton OR
James M. Dodd - Shingle Springs CA
Chung Lam - Redwood City CA
Randy M. Bonella - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 506

US Classification:

365 63, 365 51, 365 52, 36523003

Abstract:

Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.

US Patent:

6625687, Sep 23, 2003

Filed:

Sep 18, 2000

Appl. No.:

09/665238

Inventors:

John B. Halbert - Beaverton OR
Jim M. Dodd - Shingle Springs CA
Chung Lam - Redwood Shores CA
Randy M. Bonella - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711105, 711101, 711104, 711115, 711167, 711170, 365 51, 365 52, 365 63

Abstract:

A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.

US Patent:

6658509, Dec 2, 2003

Filed:

Oct 3, 2000

Appl. No.:

09/678638

Inventors:

Randy M. Bonella - Portland OR
John B. Halbert - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710100, 710300, 370223

Abstract:

Methods and apparatus for a memory system using a ring memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains point-to-point bus connections with each of two memory modules; the two modules maintain a third point-to-point bus connection between themselves, such that the three connections together form a ring bus. When data is sent from the controller to a module, half of the data is sent to the module in one direction along the ring and half is sent in the other direction, through the other module. Reverse bus communications from the module to the controller follow the reverse of these paths. This allows the bus to be half the width as it would otherwise be. In an alternate embodiment, each module contains two banks of memory that are arranged in a second ring bus local to the module. This can double the density of devices mounted on a module, while reducing pin count and simplifying signal routing on the module.

US Patent:

6697888, Feb 24, 2004

Filed:

Sep 29, 2000

Appl. No.:

09/675304

Inventors:

John B. Halbert - Beaverton OR
Jim M. Dodd - Shingle Springs CA
Chung Lam - Redwood City CA
Randy M. Bonella - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 300

US Classification:

710 52, 710 54, 710301, 711105

Abstract:

Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The buffers allow the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffers. The second sub-interface is between the buffers and the memory modules. The method also includes interleaving output of the buffers, and configuring the buffers to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

US Patent:

6742098, May 25, 2004

Filed:

Oct 3, 2000

Appl. No.:

09/678751

Inventors:

John B. Halbert - Beaverton OR
James M. Dodd - Shingle Springs CA
Chung Lam - Redwood City CA
Randy M. Bonella - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711172, 711 5, 711165, 710307, 36523005

Abstract:

Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

US Patent:

6747887, Jun 8, 2004

Filed:

Oct 2, 2002

Appl. No.:

10/263995

Inventors:

John B. Halbert - Beaverton OR
Randy M. Bonella - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 502

US Classification:

365 51, 365 52, 365 63

Abstract:

The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.