John R Halbert

US Patent:

7260007, Aug 21, 2007

Filed:

Mar 30, 2005

Appl. No.:

11/093905

Inventors:

Sandeep Jain - Milpitas CA, US
David Wyatt - San Jose CA, US
Jun Shi - San Jose CA, US
Animesh Mishra - Pleasanton CA, US
John Halbert - Beaverton OR, US
Melik Isbara - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 5/06
G11C 7/04
G11C 7/00

US Classification:

365212, 365211, 365227, 365 72, 365 63, 365 51

Abstract:

Thermal management and communication is described in the context of memory modules that contain several memory devices. In one example, the invention includes determining a temperature of a first memory device, the first memory device containing a plurality of memory cells, determining a temperature of a second memory device after determining the temperature of the first memory device, the second memory device containing a plurality of memory cells, and generating an alarm based on an evaluation of the first and the second temperatures. In another example, the invention includes detecting a thermal event on a memory device of a memory module that contains a plurality of memory devices, detecting the state of an event bus of the memory module, and sending an alert on the event bus if the event bus is in an unoccupied state.

US Patent:

7342841, Mar 11, 2008

Filed:

Dec 21, 2004

Appl. No.:

11/019881

Inventors:

Sandeep K. Jain - Milpitas CA, US
Animesh Mishra - Pleasanton CA, US
John B. Halbert - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 7/00

US Classification:

365222, 36523003, 711106

Abstract:

A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

US Patent:

7450456, Nov 11, 2008

Filed:

May 10, 2007

Appl. No.:

11/801909

Inventors:

Sandeep Jain - Milpitas CA, US
David Wyatt - San Jose CA, US
Jun Shi - San Jose CA, US
Animesh Mishra - Pleasanton CA, US
John Halbert - Beaverton OR, US
Melik Isbara - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 7/04
G11C 5/06

US Classification:

365212, 365211, 36518902, 36518907, 365227, 365228, 365 51, 365 63

Abstract:

The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

US Patent:

8289797, Oct 16, 2012

Filed:

Oct 31, 2007

Appl. No.:

11/932470

Inventors:

Sandeep K Jain - Milpitas CA, US
Animesh Mishra - Pleasanton CA, US
John B Halbert - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 11/406

US Classification:

365222, 711105, 711106, 365149

Abstract:

A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

US Patent:

20060236042, Oct 19, 2006

Filed:

Mar 31, 2005

Appl. No.:

11/096271

Inventors:

Sandeep Jain - Milpitas CA, US
John Halbert - Beaverton OR, US
Nilesh Shah - Folsom CA, US

International Classification:

G06F 13/00

US Classification:

711154000

Abstract:

Data is transmitted from a memory device along with a training sequence to deswizzle the data. The training sequence may be sent, for example, when the memory device is initialized, or it may be appended to the data. A memory controller may include logic to receive the data and training sequence and deswizzle the data in response to the training sequence to identify the location of data on various signal lines. Other embodiments are described and claimed.

US Patent:

20070005836, Jan 4, 2007

Filed:

Jun 7, 2005

Appl. No.:

11/148160

Inventors:

Sandeep Jain - Milpitas CA, US
George Vergis - Hillsboro OR, US
John Halbert - Beaverton OR, US
Nilesh Shah - Folsom CA, US

International Classification:

G06F 13/38

US Classification:

710062000

Abstract:

Swizzle information for signal lines on a memory component may be stored on the memory component. The swizzle information may be transmitted to a memory controller which may include logic to receive the swizzle information which is then used to deswizzle data received from the memory component. Data may be transmitted from a memory device to a memory controller in a format that is tolerant of swizzling on signal lines between the device and the controller. The format may include codes having unique of numbers of values. Data may be sent in multi-code bursts that divide a data range into progressively smaller ranges. Other embodiments are described and claimed.

US Patent:

20130313709, Nov 28, 2013

Filed:

Dec 22, 2011

Appl. No.:

13/994919

Inventors:

Todd A. Hinck - Arlington MA, US
Zuoguo Wu - San Jose CA, US
Aaron Martin - El Dorado Hills CA, US
Andrew W. Martwick - Portland OR, US
John B. Halbert - Beaverton OR, US

International Classification:

H01L 25/065

US Classification:

257738, 257786

Abstract:

Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package.

US Patent:

20200260556, Aug 13, 2020

Filed:

Feb 26, 2018

Appl. No.:

16/487802

Inventors:

- Milpitas CA, US
Erich R. Klawuhn - Los Altos CA, US
Brandon Tinianov - Santa Clara CA, US
Nitesh Trikha - Pleasanton CA, US
John Gordon Halbert Mathew - Santa Rosa CA, US

International Classification:

H05B 47/11
H05B 45/22
G02F 1/157
F21V 23/04
H05B 47/115
G02F 1/163
G02F 1/1523

Abstract:

A method of automatically controlling color of light in a room having one or more tintable windows, the method comprising determining adjustments in artificial interior lighting in the room to obtain a desired color of light and sending control signals over a communication network to adjust the artificial interior lighting, wherein the adjustments are determined based on a current tint state of each of the one or more tintable windows.