John Francis Irwin

Address:

6024 Riverview Way, Houston, TX 77057

Phone:

(713)7846221

VIN:

1G1YG3DWXC5108186

Make:

CHEVROLET

Model:

CORVETTE

Year:

2012

Address:

12328 Blf Shr Dr, Knoxville, TN 37922

VIN:

5TDBY64A58S009129

Make:

TOYOTA

Model:

SEQUOIA

Year:

2008

Address:

13225 Crystal Way, Austin, TX 78737

Phone:

(512)2883235

VIN:

1GCHK29637E596329

Make:

CHEVROLET

Model:

SILVERADO 2500HD

Year:

2007

Address:

2504 Legion Dr, Knoxville, TN 37920

VIN:

1GKFK63807J315964

Make:

GMC

Model:

YUKON

Year:

2007

US Patent:

46959459, Sep 22, 1987

Filed:

Feb 28, 1985

Appl. No.:

6/706802

Inventors:

John W. Irwin - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1516

US Classification:

364200

Abstract:

A co-processor is connectable to a main system data bus to run software unknown to the main processor. The main processor can concurrently run other software and maintains priority over shared I/O facilities by providing trapping logic incorporated in a random access memory and dynamically loadable by the master processor which contains data related to the current useability by the co-processor of a shared I/O device. Additional logic is associated with the co-processor to manage interrupts between the co-processor and the system bus.

US Patent:

48598151, Aug 22, 1989

Filed:

Dec 19, 1988

Appl. No.:

7/285921

Inventors:

John W. Irwin - Austin TX
James D. Wagoner - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 110
H04L 2549

US Classification:

178 69D

Abstract:

In a serial link in which it is necessary to occupy the link before and after transmission of a frame by sending a succession idle characters having alternating disparity effects, the disparity effect of the last character in the frame is compared with the disparity effect that would be produced by a disparity flip-flop, which has continued to step during frame transmission. If the disparity effect of these two characters match, no corrective action is required in order to resume the stream of idle characters. If the disparity effect of these characters differ, the disparity flip-flop is corrected before the stream of idle characters is resumed. Disclosed is hardware logic to accomplish this disparity control following transmission of frames in a transparent mode.

US Patent:

50088165, Apr 16, 1991

Filed:

Nov 6, 1987

Appl. No.:

7/117715

Inventors:

Richard G. Fogg - Austin TX
John W. Irwin - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200
G06F 1516
G06F 1310

US Classification:

364200

Abstract:

A memory system that includes several memory locations connected to a reading circuit that provides read access to the memory location. The memory system also includes the controller that receives control information. A writing circuit is further included that provides write access to either only a first portion of the memory locations, or simultaneously several portions of the memory locations is designated by the control information. This invention further includes a memory system that provides several memory locations for the storage of information together with the controller having a first port and a second port. The first port provides access to the memory locations in response to a first address range and the second port provides access to the memory locations in response to several address ranges wherein at least one of the address ranges of the second port is different then the address range of the first port. Still further, the invention includes a memory system having a first group of memory locations that store information in accordance with the first address range and a second group of memory locations. The two groups of memory locations are connected to a controller that provides write access to the first group of memory locations in a response to write commands having addresses within the first address range and, simultaneously writing each write command address in the second group of memory locations.

US Patent:

47574410, Jul 12, 1988

Filed:

Jun 29, 1987

Appl. No.:

7/068769

Inventors:

Patrick A. Buckland - Austin TX
John W. Irwin - Georgetown TX
Jack E. Reeder - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1310
G06F 1516

US Classification:

364200

Abstract:

A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. The display control means is based on logic circuitry associated with the co-processor for trapping instructions having addresses within the range of those reserved for the display devices. The logic enables normal writes and reads to the video buffer to be suppressed or relocated to the virtual buffer, depending on the mode established by the main processor. A circular queue is established in memory to enable the main processor to selectively individually update the video buffer with the changes that have been made to the virtual buffer.

US Patent:

47034203, Oct 27, 1987

Filed:

Feb 28, 1985

Appl. No.:

6/706804

Inventors:

John W. Irwin - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1318

US Classification:

364200

Abstract:

A data processing system having a main processing unit, a memory subsystem, and a co-processor selectively connectable to said memory subsystem through an Input/Output Channel Controller which includes a control means for arbitrating access to the I/O Bus among the co-processor and the other I/O devices connected to the Bus. Since the co-processor runs programs stored in the memory subsystem, there is a tendency for the co-processor to monopolize the bus with instruction fetch cycles, thereby excluding other I/O devices from access to the bus. The control means for arbitrating responds to requests on the basis of a linear priority scheme in which the co-processor has the lowest priority. Each device, except the co-processor, is permitted to keep control of the bus until it voluntarily relinquishes it. The co-processor, on the other hand, relinquishes control of the bus in response to a request for access by any higher operator.

US Patent:

48335967, May 23, 1989

Filed:

Mar 23, 1988

Appl. No.:

7/172042

Inventors:

Patrick A. Buckland - Austin TX
John W. Irwin - Georgetown TX
Jack E. Reeder - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1310
G06F 1516

US Classification:

364200

Abstract:

A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. In a second mode, a display is time-shared between processors by establishing a virtual video buffer in main memory which is written into by one processor when the other processor has control of the display device. The contents of the virtual and real buffer are swapped whenever the display is reassigned to the other processor. In the third mode, co-processor data in the virtual buffer can be "windowed" onto the display device when it is assigned to the main processor.

US Patent:

44969546, Jan 29, 1985

Filed:

Dec 16, 1982

Appl. No.:

6/450416

Inventors:

John W. Irwin - Georgetown TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01D 1518

US Classification:

346 11

Abstract:

Optimal reservoing times of an ink jet printer are determined to be when an optimal time period exceeds a fixed maximum value, where the optimal time period is proportional: to the time since last reservoing, to the usage, and to the square of temperature changes. Specifically, the optimal time period, t-opt, is t-opt=T+mC+kKK where T=time since last reservoing, C=usage value, K=temperature changes, and m,k=empirically-determined constants.