John K Li

US Patent:

7783864, Aug 24, 2010

Filed:

Feb 12, 2007

Appl. No.:

11/673752

Inventors:

Camil Fayad - Poughkeepsie NY, US
John K. Li - Woodstock NY, US
Siegfried Sutter - Elsendorf, DE
Tamas Visegrady - Zurich, CH

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/44
G06F 7/38

US Classification:

712221, 708491

Abstract:

The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of simultaneous operation in two subphases per processing element and the chaining together of processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a pardonable chain with separate parts for processing factors of the modulus.

US Patent:

7818574, Oct 19, 2010

Filed:

Sep 10, 2004

Appl. No.:

10/938808

Inventors:

Camil Fayad - Poughkeepsie NY, US
John K. Li - Woodstock NY, US
Siegfried Sutter - Boeblingen, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 9/32

US Classification:

713175, 713173, 713192, 713194, 713156, 726 27, 726 34

Abstract:

A mechanism is provided in which access to the functionality present on an integrated circuit chip is controllable via an encrypted certificate of authority which includes time information indicating allowable periods of operation or allowable duration of operation. The chip includes at least one cryptographic engine and at least one processor. The chip also contains hard coded cryptographic keys including a chip private key, a chip public key and a third party's public key. The chip is also provided with a battery backed up volatile memory which contains information which is used to verify authority for operation. The certificate of authority is also used to control not only the temporal aspects of operation but is also usable to control access to certain functionality that may be present on the chip, such as access to some or all of the cryptographic features provided in conjunction with the presence of the cryptographic engine, such as key size.

US Patent:

7870395, Jan 11, 2011

Filed:

Oct 20, 2006

Appl. No.:

11/551432

Inventors:

Thomas J. Dewkett - Staatsburg NY, US
Camil Fayad - Poughkeepsie NY, US
John K. Li - Woodstock NY, US
Siegfried K. H. Sutter - Elsendorf, DE
Phil C. Yeh - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/14
G06F 15/167
G06F 15/80
G06F 15/82

US Classification:

713189, 713190, 713192, 713193, 709215, 712 10, 712 13, 712 17, 712 27

Abstract:

In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.

US Patent:

7873830, Jan 18, 2011

Filed:

Jan 13, 2006

Appl. No.:

11/331918

Inventors:

Camil Fayad - Poughkeepsie NY, US
John K. Li - Woodstock NY, US
Siegfried Sutter - Boeblingen, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 9/32
G06F 9/50
G06F 15/167
G06F 13/00

US Classification:

713169, 713189, 713193, 711150, 711153, 711147, 709213, 709215, 380277

Abstract:

Electronic circuit chips which include cryptography functions are arranged in multichip configurations through the utilization of a shared external memory. Security of the chips is preserved via a handshaking protocol which permits each chip to access limited portions of the memory as defined in a way that preserves the same high security level as the tamper proof chips themselves. The chips may be operated to work on different tasks or to work on the same task thus providing a mechanism for trading off speed versus redundancy where desired.

US Patent:

7890559, Feb 15, 2011

Filed:

Dec 22, 2006

Appl. No.:

11/615587

Inventors:

Camil Fayad - Poughkeepsie NY, US
John K. Li - Woodstock NY, US
Siegfried K. H. Sutter - Elsendorf, DE
Tamas Visegrady - Zurich, CH

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/00

US Classification:

708233

Abstract:

A data processing system, which is particularly useful for carrying out modular multiplication, especially for cryptographic purposes, comprises a plurality of independent, serially connected processing elements which are provided with data in a cyclical fashion via a control mechanism that is capable of transferring data from a set of registers to earlier ones in the series of the serially connected processing elements, at the end of a predetermined number of cycles.

US Patent:

8532288, Sep 10, 2013

Filed:

Dec 1, 2006

Appl. No.:

11/565918

Inventors:

Camil Fayad - Poughkeepsie NY, US
John K. Li - Woodstock NY, US
Siegfried K. H. Sutter - Elsendorf, DE
Phil C. Yeh - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 21/00

US Classification:

380 44, 380 45, 380 46, 380 47, 380 28, 380 29, 380 30, 712 1, 712 7, 712 9, 712 10, 712 11, 712 12, 712 13, 712 14, 712 15, 712 16, 712 17, 712 20, 712 21, 712 22

Abstract:

A cryptographic engine for modulo N multiplication, which is structured as a plurality of almost identical, serially connected Processing Elements, is controlled so as to accept input in blocks that are smaller than the maximum capability of the engine in terms of bits multiplied at one time. The serially connected hardware is thus partitioned on the fly to process a variety of cryptographic key sizes while still maintaining all of the hardware in an active processing state.

US Patent:

20060059368, Mar 16, 2006

Filed:

Sep 10, 2004

Appl. No.:

10/938834

Inventors:

Camil Fayad - Poughkeepsie NY, US
John Li - Woodstock NY, US
Siegfried Sutter - Boeblingen, DE

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H04L 9/00
G06F 12/14
H04L 9/32
G06F 11/30

US Classification:

713189000, 713172000

Abstract:

A system and method are provided in which a third party chip vendor is enabled to securely program an electronic circuit chip supplied from a chip manufacturer. The chip vendor supplies a vendor's public cryptography key to the chip manufacturer who hard codes it on the chip along with a chip private key and a chip public key. One or more cryptographic engines on the chip, which preferably has a tamper resistant/detecting boundary, are used to decrypt program instructions supplied to the chip after having been encrypted with the vendor's private key and the chip public key. The chip includes a processor and an associated memory which receives a version of the instructions decrypted with the chip private key and the vendor's public key. The chip also preferably includes programmable hardware which is also securely programmable by the downstream chip vendor. The chip, as processed by the chip vendor is shipped with a battery in place to provide power for maintaining data held in volatile memory portions of the chip.

US Patent:

20060059369, Mar 16, 2006

Filed:

Sep 10, 2004

Appl. No.:

10/938835

Inventors:

Camil Fayad - Poughkeepsie NY, US
John Li - Woodstock NY, US
Siegfried Sutter - Boeblingen, DE

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 12/14
H04L 9/32
G06F 11/30

US Classification:

713189000, 713190000

Abstract:

A mechanism is provided in which a secure chip for performing cryptographic and/or other functions is able to securely access a separate random access memory externally disposed with respect to a secure chip boundary. Addressing of the external memory is controlled so as to define certain regions therein which receive and store only encrypted information from the chip. Other regions of the external memory are set aside for the receipt and storage of unencrypted information. Access to the external memory is provided through a controlled interface which communicates with internal chip hardware which operates to control the flow of communication between various internal components such as cryptographic engines, data processors, internal memory of both the volatile and the nonvolatile variety and an external interface which provides the only other access to the chip. The internal chip hardware with which the external memory interface communicates is implemented as a combined ASIC and programmable hardware circuit, wherein the programmable hardware circuit is also securely configurable.