John Tlawng Lin

US Patent:

7141455, Nov 28, 2006

Filed:

Nov 12, 2003

Appl. No.:

10/712455

Inventors:

Binghua Hu - Plano TX, US
Howard S. Lee - Plano TX, US
Henry L. Edwards - Garland TX, US
John Lin - Chelmsford MA, US
Vladimir N. Bolkhovsky - Framingham MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/332

US Classification:

438135, 438306, 438305

Abstract:

A double diffused region (), (), () is formed in an epitaxial layer (). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer () is formed on the epitaxial layer () and gate structures (), () are formed over the dielectric layer ().

US Patent:

7345343, Mar 18, 2008

Filed:

Aug 2, 2005

Appl. No.:

11/195283

Inventors:

Tony T. Phan - Flower Mound TX, US
William C. Loftin - Plano TX, US
John Lin - Chelmsford MA, US
Philip L. Hower - Concord MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/84

US Classification:

257347, 438149

Abstract:

The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate ().

US Patent:

7696049, Apr 13, 2010

Filed:

Oct 24, 2006

Appl. No.:

11/552198

Inventors:

Binghua Hu - Plano TX, US
Howard S. Lee - Plano TX, US
Henry L. Edwards - Garland TX, US
John Lin - Chelmsford MA, US
Vladimir N. Bolkhovsky - Framingham MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/00

US Classification:

438289, 438297, 438301

Abstract:

A double diffused region (), (), () is formed in a semiconductor substrate or in an epitaxial layer () formed on the semiconductor substrate. The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to the hard bake process, a heavy implant species such as arsenic is implanted into the epitaxial layer. During subsequent processing, such as during LOCOS formation, a double diffused region is formed by a thermal anneal. A dielectric layer () is formed on the epitaxial layer () and gate structures (), () are formed over the dielectric layer ().

US Patent:

7741205, Jun 22, 2010

Filed:

Jan 18, 2008

Appl. No.:

12/016443

Inventors:

Tony Thanh Phan - Flower Mound TX, US
William C Loftin - Plano TX, US
John Lin - Chelmsford MA, US
Philip L Hower - Concord MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/768

US Classification:

438597, 257E21575

Abstract:

The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate ().

US Patent:

7846789, Dec 7, 2010

Filed:

Oct 16, 2007

Appl. No.:

11/873205

Inventors:

Sameer P. Pendharkar - Allen TX, US
John Lin - Chelmsford MA, US
Philip L. Hower - Concord MA, US
Steven L. Merchant - Amherst NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8238

US Classification:

438202, 438234, 438294, 438296, 438700, 257E2154, 257E21642, 257E21696

Abstract:

A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.

US Patent:

8274131, Sep 25, 2012

Filed:

Dec 7, 2010

Appl. No.:

12/962159

Inventors:

Sameer P. Pendharkar - Allen TX, US
John Lin - Chelmsford MA, US
Philip L. Hower - Concord MA, US
Steven L. Merchant - Amherst NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/70

US Classification:

257501, 257378, 257E21696

Abstract:

A semiconductor device comprising a first transistor device () on or in a semiconductor substrate () and a second transistor device () on or in the substrate. The device further comprises an insulating trench () located between the first transistor device and the second transistor device. At least one upper corner () of the insulating trench is a rounded corner in a lateral plane () of the substrate.

US Patent:

20100264486, Oct 21, 2010

Filed:

Apr 20, 2009

Appl. No.:

12/426717

Inventors:

Marie Denison - Plano TX, US
Sameer Pendharkar - Allen TX, US
Philip L. Hower - Concord MA, US
John Lin - Chelmsford MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/78
H01L 21/28
H01L 21/336

US Classification:

257330, 438589, 438270, 257E29262, 257E2141, 257E2119

Abstract:

An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.

US Patent:

20110275210, Nov 10, 2011

Filed:

Jul 21, 2011

Appl. No.:

13/188162

Inventors:

Marie Denison - Plano TX, US
Sameer Pendharkar - Allen TX, US
Philip L. Hower - Concord MA, US
John Lin - Chelmsford MA, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01L 21/28

US Classification:

438589, 257E2119

Abstract:

An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.