John H Lo

US Patent:

5488332, Jan 30, 1996

Filed:

Jun 10, 1994

Appl. No.:

8/258347

Inventors:

John De Lo - Decatur GA

Assignee:

Oki Telecom - Suwanee GA

International Classification:

H03L 708
H03L 7085
H03L 718

US Classification:

331 25

Abstract:

A phase-locked loop (PLL) frequency synthesizer is connected in reverse to a reference signal and a controlled oscillator loop including a low pass filter and a voltage-controlled oscillator (VCO). Rather than receiving a reference signal through a reference oscillator input and a VCO output signal through a VCO input, the PLL frequency synthesizer receives a reference signal through the VCO input and receives the VCO output signal through the reference oscillator input. Additionally, the output of the PLL is taken from the buffered reference output, thereby eliminating the need for an external buffer. Accordingly, the data loaded into the PLL frequency synthesizer accommodates the reversed input scheme by altering the divide ratios and inverting the phase detector output signal. In addition, a selective grounding network is connected to the reference oscillator input of the PLL frequency synthesizer to greatly reduce power consumption of the PLL frequency synthesizer, and as part of the same effort, a voltage switch is utilized to remove power to the VCO.

US Patent:

5602513, Feb 11, 1997

Filed:

Jun 6, 1995

Appl. No.:

8/466222

Inventors:

John De Lo - Decatur GA

Assignee:

Oki Telecom - Suwanee GA

International Classification:

H03L 708
H03L 7085

US Classification:

331 25

Abstract:

A phase-locked loop (PLL) frequency synthesizer is connected in reverse to a reference signal and a controlled oscillator loop including a low pass filter and a voltage-controlled oscillator (VCO). Rather than receiving a reference signal through a reference oscillator input and a VCO output signal through a VCO input, the PLL frequency synthesizer receives a reference signal through the VCO input and receives the VCO output signal through the reference oscillator input. Additionally, the output of the PLL is taken from the buffered reference output, thereby eliminating the need for an external buffer. Accordingly, the data loaded into the PLL frequency synthesizer accommodates the reversed input scheme by altering the divide ratios and inverting the phase detector output signal. In addition, a selective grounding network is connected to the reference oscillator input of the PLL frequency synthesizer to greatly reduce power consumption of the PLL frequency synthesizer, and as part of the same effort, a voltage switch is utilized to remove power to the VCO.

US Patent:

5603113, Feb 11, 1997

Filed:

Feb 9, 1995

Appl. No.:

8/386080

Inventors:

John De Lo - Decatur GA

Assignee:

Oki telecom - Suwanee GA

International Classification:

H04B 7005

US Classification:

4552341

Abstract:

A closed loop AGC circuit for a digital side of a dual mode cellular telephone wherein receiver and transmitter adjustable amplifiers are controlled by a linear feedback control system including a linear signal level detector which determines signal levels after a receiver baseband demodulator stage. The linear signal level detector receives a signal at an AC signal level and produces, through an averaging process, a DC received signal strength indication at a DC signal level which is linearly proportional to the AC signal level. The received signal strength indication is compared to a reference signal to produce a gain control signal which is linearly inverted and supplied as a receive gain control signal to the receiver adjustable amplifiers. The gain control signal is also combined with a transmit adjust signal received from the base station and supplied as a transmit gain control signal to the transmitter adjustable amplifiers.

US Patent:

5649288, Jul 15, 1997

Filed:

Jun 6, 1995

Appl. No.:

8/468019

Inventors:

John De Lo - Decatur GA
He Feng Wang - Saitama, JP

Assignee:

OKI telecom - Suwanee GA

International Classification:

H04Q 700
H04Q 900

US Classification:

455 331

Abstract:

A circuit for connecting multiple signal paths within a multi-mode communication device includes a double balanced mixer circuit selectively functioning as a modulation switch during an unbalanced state. As applied to a transmit section of a CDMA/FM cellular telephone, a dual-function double balanced mixer circuit connects a CDMA IF signal path with an FM audio signal path. The double balanced mixer circuit includes a double balanced mixer connected through oscillator input to an external LC (inductor-capacitor) tank connected to both a PLL (phase lock loop) and an FM audio signal. One signal input of the double balanced mixer receives a CDMA low IF signal, while the other double balanced mixer signal input is connected to a microprocessor-controlled switch for selectively unbalancing the balanced mixer while in the FM mode of operation.

US Patent:

5893030, Apr 6, 1999

Filed:

May 25, 1994

Appl. No.:

8/249261

Inventors:

John De Lo - Decatur GA
He Feng Wang - Saitama, JP

Assignee:

Oki Telecom

International Classification:

H04B 126

US Classification:

455326

Abstract:

A circuit for connecting multiple signal paths within a multi-mode communication device includes a double balanced mixer circuit selectively functioning as a modulation switch during an unbalanced state. As applied to a transmit section of a CDMA/FM cellular telephone, a dual-function double balanced mixer circuit connects a CDMA IF signal path with an FM audio signal path. The double balanced mixer circuit includes a double balanced mixer connected through oscillator input to an external LC (inductor-capacitor) tank connected to both a PLL (phase lock loop) and an FM audio signal. One signal input of the double balanced mixer receives a CDMA low IF signal, while the other double balanced mixer signal input is connected to a microprocessor-controlled switch for selectively unbalancing the balanced mixer while in the FM mode of operation.