John D Lockhart

US Patent:

39874478, Oct 19, 1976

Filed:

Jun 21, 1965

Appl. No.:

4/465805

Inventors:

John C. Lockhart - Oreland PA
Standish C. Hartman - Flemington NJ
Carl F. Mattes - Levittown PA
Bruce R. Meuron - Willow Grove PA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H04B 700

US Classification:

343228

Abstract:

A command data link between an aircraft and a missile having a high invulability to jamming by providing a communications system in which the missile receiver is normally off and is gated on only during a short time during which a signal is supposed to appear, as determined by the missile synchronizer. Coded information is transmitted to the missile by the absence of pulses in a pulse train so that spurious pulses received by the missile cannot result in undesirable missile commands.

US Patent:

50041851, Apr 2, 1991

Filed:

Aug 31, 1964

Appl. No.:

4/394388

Inventors:

John C. Lockhart - Oreland PA
Standish C. Hartman - Flemington NJ
Bruce R. Meuron - Willow Grove PA
Joseph B. Lyons - Philadelphia PA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

F41G 700

US Classification:

224 314

Abstract:

This invention relates to an aircraft missile communication system comprig means to generate a digital sequence corresponding to command signals, means in the aircraft to mix the digital command sequence with the code sequence and transmit the combination to an object; means to compare the received code sequence with the second digital code sequence and means in said object depended upon the comparing means to express said digital command sequence.

US Patent:

50220799, Jun 4, 1991

Filed:

Aug 31, 1964

Appl. No.:

4/394389

Inventors:

John C. Lockhart - Oreland PA

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H04N 7167

US Classification:

380 14

Abstract:

1. A digital code synchronization locking means comprising: means to receive a first digital code sequence; means to generate a second digital code sequence substantially similar to id first sequence, said means to generate said (second) digital code sequence including: a shift register having an output from a predetermined stage thereof; a feedback logic matrix connected to said shift register for generating said second digital code sequence; a binary pulse counter, the last stage of which provides a reset pulse to all the stages of said shift register; means to detect drift from synchronization of said second code sequence with said first code sequence one stage before said predetermined stage and one stage after said predetermined stage; a clock oscillator providing clock pulses to all stages of said shift register and to the first stage of said binary counter; and an oscillator control connected to said clock oscillator and responsive to said means to detect drift for advancing the rate of said clock oscillator upon correlation of said first code sequence with said one stage before said predetermined stage and retarding the rate of said clock oscillator upon correlation of said first code sequence with said one stage after said predetermined stage, whereby said second code sequence is maintained in synchronization with said first code sequence.