John J Mead

US Patent:

7461197, Dec 2, 2008

Filed:

Dec 19, 2005

Appl. No.:

11/311728

Inventors:

Bob R. Southerland - Longmont CO, US
John Mead - Longmont CO, US
Kevin W. McGinnis - Berthoud CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 12/00

US Classification:

711 4, 711111, 711154, 711200, 360 7704

Abstract:

A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

US Patent:

7474487, Jan 6, 2009

Filed:

Dec 19, 2005

Appl. No.:

11/311726

Inventors:

Bob R. Southerland - Longmont CO, US
John Mead - Longmont CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11B 5/09

US Classification:

360 51

Abstract:

A read/write timing generator includes a read/write signal generator for generating a read/write signal in response to the media event trigger of a disk drive and synchronized to a read/write bit clock. A read/write symbol clock generator adjusts a read/write symbol clock based on the read/write signal and the read/write bit clock.

US Patent:

7529052, May 5, 2009

Filed:

Dec 19, 2005

Appl. No.:

11/311725

Inventors:

John Mead - Longmont CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11B 5/09

US Classification:

360 51

Abstract:

A disk controller includes a write signal generator for generating a write gate signal based on a media event trigger. A read signal generator generates a read gate signal based on the media event trigger and a read/write bit clock. A read/write channel, adjusts the read gate signal based on the read/write bit clock to avoid a write splice period.

US Patent:

7538962, May 26, 2009

Filed:

Dec 19, 2005

Appl. No.:

11/311727

Inventors:

John Mead - Longmont CO, US
William Bliss - Thornton CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11B 5/09

US Classification:

360 51, 360 48, 360 53

Abstract:

A media event timer includes a counter module for generating a sequence of counts based on a clock signal of a disk drive unit. A counter reset module sets the counter module to a reset count in response to a servo address mark detection signal. A detector module detects that a servo address mark has been missed and sets the counter module to a restart count when the servo address mark has been missed. A trigger module triggers a first media event when a first media event count compares favorably to a count of the sequence of counts.

US Patent:

7587538, Sep 8, 2009

Filed:

Jun 1, 2006

Appl. No.:

11/444821

Inventors:

Lance Flake - Longmont CO, US
John P. Mead - Longmont CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 13/12

US Classification:

710 74, 360 46, 360 48

Abstract:

A channel interface couples a channel circuit to a controller circuit of a disk drive, the channel circuit includes a channel register and the controller circuit includes a controller register used in the execution of read and write commands. The channel interface includes a bidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer disk read data and disk write data, to provide the controller circuit access to read from, and write to, the channel register, and to provide the channel circuit access to read from, and write to, the controller register. The channel interface further includes a first unidirectional transmission path between the controller circuit and the channel circuit that is operable to transfer servo data from the channel circuit to the controller circuit.

US Patent:

7600176, Oct 6, 2009

Filed:

Apr 27, 2006

Appl. No.:

11/412390

Inventors:

John P. Mead - Longmont CO, US
Kevin W. McGinnis - Berthoud CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 13/00

US Classification:

714784, 714756, 714757, 714769

Abstract:

Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A means is presented by which multiple Galois field computations are performed in parallel with one another. Processor, memory, and plurality of adders and/or multipliers are implemented appropriately to allow parallel Galois field computations to be performed. Multiplexing can be performed to govern the writing of resultants (generated using the adders and/or multipliers) back to the memory via feedback paths. This approach allows for parallel (as opposed to serial) implementation of the software ECC corrections with minimal area and power impact. In other words, very little space is required to implement this approach is hardware with nominal increase in power consumption, and this slight increase in power consumption provides a significant increase in ECC correction capability using this approach.

US Patent:

7620772, Nov 17, 2009

Filed:

Oct 19, 2006

Appl. No.:

11/583331

Inventors:

Bruce A. Liikanen - Berthoud CO, US
Mike L. Mallary - Sterling MA, US
John Mead - Longmont CO, US
Eric D. Mudama - Longmont CO, US
John W. VanLaanen - Louisville CO, US
Andrew W. Vogan - Portland OR, US

Assignee:

Seagate Technology, LLC - Scotts Valley CA

International Classification:

G06F 12/00

US Classification:

711112, 711154, 711170, 711173, 711202

Abstract:

Methods and structures for dynamic density control to improve reliability of a dynamically mapped storage device. In a dynamically mapped storage device in which all user supplied logical blocks are dynamically mapped by the storage device controller to physical disk blocks, features and aspects hereof provide for dynamically altering the recording density of user data stored on the storage device. So long as the physical capacity utilization of the storage device permits, new data stored on the device may be stored at lower density to improve reliability in reading back the recorded data. Further features and aspects hereof may reduce the recording density only for data deemed to be critical. Radial (track) density, longitudinal (bit) density, or both may be dynamically controlled to reduce recording density. As physical capacity utilization increases, data previously recorded at lower density may be migrated (re-recorded) at normal higher density.

US Patent:

7661057, Feb 9, 2010

Filed:

Feb 17, 2006

Appl. No.:

11/356812

Inventors:

Kevin W. McGinnis - Berthoud CO, US
John P. Mead - Longmont CO, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03M 13/15

US Classification:

714784

Abstract:

Clocking Chien searching at different frequency than other Reed-Solomon (RS) ECC decoding functions. An efficient implementation allows for a fast clock signal to govern the operation of the more computationally and time-intensive portions of the error correction code (ECC) time budget. For example, at least one module and/or decoding function within the ECC decoding is governed by using a first clock signal, and at least one other module and/or decoding function (or all the other modules and/or decoding functions) is/are governed by using a second clock signal. In one implementation of Reed-Solomon (RS) decoding, the Chien searching function is operated using a faster clock signal than at least one other RS error correction decoding function thereby allowing for a significant reduction in area and power than other architectural trade-offs.