John F Patrick

US Patent:

7243195, Jul 10, 2007

Filed:

Dec 2, 2004

Appl. No.:

11/002553

Inventors:

John Kevin Patrick O'Brien - South Salem NY, US
Kathryn M. O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711159, 711118, 711165

Abstract:

The present invention provides for a method for computer program code optimization for a software managed cache in either a uni-processor or a multi-processor system. A single source file comprising a plurality of array references is received. The plurality of array references is analyzed to identify predictable accesses. The plurality of array references is analyzed to identify secondary predictable accesses. One or more of the plurality of array references is aggregated based on identified predictable accesses and identified secondary predictable accesses to generate aggregated references. The single source file is restructured based on the aggregated references to generate restructured code. Prefetch code is inserted in the restructured code based on the aggregated references. Software cache update code is inserted in the restructured code based on the aggregated references.

US Patent:

7386842, Jun 10, 2008

Filed:

Jun 7, 2004

Appl. No.:

10/862483

Inventors:

Alexandre E. Eichenberger - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Peng Wu - Mt. Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45

US Classification:

717150, 717160

Abstract:

An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then inserts data reorganization operations to satisfy the actual alignment requirement of the hardware. Finally, the code generation algorithm generates SIMD codes based on the data reorganization graph, addressing realistic issues such as runtime alignments, unknown loop bounds, residue iteration counts, and multiple statements with arbitrary alignment combinations. Beyond generating a valid simdization, a preferred embodiment further improves the quality of the generated codes. Four stream-shift placement policies are disclosed, which minimize the number of data reorganization generated by the alignment handling.

US Patent:

7461205, Dec 2, 2008

Filed:

Jun 1, 2006

Appl. No.:

11/421505

Inventors:

John Kevin Patrick O'Brien - South Salem NY, US
Kathryn O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 9/06
G06F 9/30
G06F 9/40

US Classification:

711118, 711125, 711123, 711133, 711154, 711165, 711213, 711215

Abstract:

Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed.

US Patent:

7478376, Jan 13, 2009

Filed:

Dec 2, 2004

Appl. No.:

11/002552

Inventors:

Kathryn M. O'Brien - South Salem NY, US
John Kevin Patrick O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45
G06F 9/46

US Classification:

717149, 717159, 718106

Abstract:

The present invention provides for a method for computer program code size partitioning for multiple memory multi-processor systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A program representation based on received computer program code is generated. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one SESE region of less than a certain size (store-size-specific) is identified based on identified SESE regions and the at least one system parameter. Each store-size-specific SESE region is grouped into a node-specific subroutine. The non node-specific parts of the computer program code are modified based on the partitioning into node-specific subroutines. The modified computer program code including each node-specific subroutine is compiled based on a specified node characteristic.

US Patent:

7487496, Feb 3, 2009

Filed:

Dec 2, 2004

Appl. No.:

11/002550

Inventors:

Kathryn M. O'Brien - South Salem NY, US
John Kevin Patrick O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45
G06F 9/46

US Classification:

717149, 717159, 718106

Abstract:

The present invention provides for a method for computer program functional partitioning for heterogeneous multi-processing systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A whole program representation is generated based on received computer program code. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one node-specific SESE region is identified based on identified SESE regions and the at least one system parameter. Each node-specific SESE region is grouped into a node-specific subroutine. Each node-specific subroutine is compiled based on a specified node characteristic. The computer program code is modified based on the node-specific subroutines and the modified computer program code is compiled.

US Patent:

7493452, Feb 17, 2009

Filed:

Aug 18, 2006

Appl. No.:

11/465522

Inventors:

Alexandre E. Eichenberger - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn M. O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711137, 711133, 711144, 711206

Abstract:

A method to efficiently pre-fetch and batch compiler-assisted software cache accesses is provided. The method reduces the overhead associated with software cache directory accesses. With the method, the local memory address of the cache line that stores the pre-fetched data is itself cached, such as in a register or well known location in local memory, so that a later data access does not need to perform address translation and software cache operations and can instead access the data directly from the software cache using the cached local memory address. This saves processor cycles that would otherwise be required to perform the address translation a second time when the data is to be used. Moreover, the system and method directly enable software cache accesses to be effectively decoupled from address translation in order to increase the overlap between computation and communication.

US Patent:

7512745, Mar 31, 2009

Filed:

Apr 28, 2006

Appl. No.:

11/380683

Inventors:

Michael K. Gschwind - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn M. O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711147, 711153, 711173, 711E12011, 707206

Abstract:

Garbage collection in heterogeneous multiprocessor systems is provided. In some illustrative embodiments, garbage collection operations are distributed across a plurality of the processors in the heterogeneous multiprocessor system. Portions of a global mark queue are assigned to processors of the heterogeneous multiprocessor system along with corresponding chunks of a shared memory. The processors perform garbage collection on their assigned portions of the global mark queue and corresponding chunk of shared memory marking memory object references as reachable or adding memory object references to a non-local mark stack. The marked memory objects are merged with a global mark stack and memory object references in the non-local mark stack are merged with a “to be traced” portion of the global mark queue for re-checking using a garbage collection operation.

US Patent:

7765360, Jul 27, 2010

Filed:

Oct 1, 2008

Appl. No.:

12/243339

Inventors:

John Kevin Patrick O'Brien - South Salem NY, US
Kathryn O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 9/06
G06F 9/30
G06F 9/40

US Classification:

711118, 711125, 711123, 711133, 711154, 711165, 711213, 711215

Abstract:

Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed.