John D Patrick

US Patent:

7386842, Jun 10, 2008

Filed:

Jun 7, 2004

Appl. No.:

10/862483

Inventors:

Alexandre E. Eichenberger - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Peng Wu - Mt. Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45

US Classification:

717150, 717160

Abstract:

An approach is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then inserts data reorganization operations to satisfy the actual alignment requirement of the hardware. Finally, the code generation algorithm generates SIMD codes based on the data reorganization graph, addressing realistic issues such as runtime alignments, unknown loop bounds, residue iteration counts, and multiple statements with arbitrary alignment combinations. Beyond generating a valid simdization, a preferred embodiment further improves the quality of the generated codes. Four stream-shift placement policies are disclosed, which minimize the number of data reorganization generated by the alignment handling.

US Patent:

7493452, Feb 17, 2009

Filed:

Aug 18, 2006

Appl. No.:

11/465522

Inventors:

Alexandre E. Eichenberger - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn M. O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711137, 711133, 711144, 711206

Abstract:

A method to efficiently pre-fetch and batch compiler-assisted software cache accesses is provided. The method reduces the overhead associated with software cache directory accesses. With the method, the local memory address of the cache line that stores the pre-fetched data is itself cached, such as in a register or well known location in local memory, so that a later data access does not need to perform address translation and software cache operations and can instead access the data directly from the software cache using the cached local memory address. This saves processor cycles that would otherwise be required to perform the address translation a second time when the data is to be used. Moreover, the system and method directly enable software cache accesses to be effectively decoupled from address translation in order to increase the overlap between computation and communication.

US Patent:

7512745, Mar 31, 2009

Filed:

Apr 28, 2006

Appl. No.:

11/380683

Inventors:

Michael K. Gschwind - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn M. O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711147, 711153, 711173, 711E12011, 707206

Abstract:

Garbage collection in heterogeneous multiprocessor systems is provided. In some illustrative embodiments, garbage collection operations are distributed across a plurality of the processors in the heterogeneous multiprocessor system. Portions of a global mark queue are assigned to processors of the heterogeneous multiprocessor system along with corresponding chunks of a shared memory. The processors perform garbage collection on their assigned portions of the global mark queue and corresponding chunk of shared memory marking memory object references as reachable or adding memory object references to a non-local mark stack. The marked memory objects are merged with a global mark stack and memory object references in the non-local mark stack are merged with a “to be traced” portion of the global mark queue for re-checking using a garbage collection operation.

US Patent:

8006238, Aug 23, 2011

Filed:

Sep 26, 2006

Appl. No.:

11/535172

Inventors:

Alexandre E. Eichenberger - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn M. O'Brien - South Salem NY, US
Tong Chen - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45
G06F 9/40
G06F 9/46

US Classification:

717150, 717149, 717160, 712204, 718102, 718104

Abstract:

A process, compiler, computer program product and system for workload partitioning in a heterogeneous system. The process includes determining heterogeneous alignment constraints in the workload, partitioning a portion of tasks to a processing element sensitive to alignment constraints, and partitioning a remaining portion of tasks to a processing element not sensitive to alignment constraints.

US Patent:

8132169, Mar 6, 2012

Filed:

Jul 21, 2006

Appl. No.:

11/459154

Inventors:

Michael Karl Gschwind - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Kathryn O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46

US Classification:

718100, 718101, 718102, 718104, 718106

Abstract:

A system and method for dividing an application into a number of logical program partitions is presented. Each of these logical program partitions are stored in a logical program package along with a execution monitor. The execution monitor runs in one of the processing environments of a heterogeneous processing environment. The logical program partition includes sets of object code for executing on each of the types of processors included in the heterogeneous processing environment. The logical program partition includes instrumentation data used to evaluate the performance of a currently executing partition. The execution monitor compares the instrumentation data to the gathered profile data. If the execution monitor determines that the partition is performing poorly then the code for the other environment is retrieved from the logical program package and loaded and executed on the other environment.

US Patent:

8146067, Mar 27, 2012

Filed:

Apr 23, 2008

Appl. No.:

12/108056

Inventors:

Alexandre E. Eichenberger - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Peng Wu - Mt. Kisco NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45

US Classification:

717150, 717160

Abstract:

Vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores is presented. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then inserts data reorganization operations to satisfy the actual alignment requirement of the hardware. Finally, the code generation algorithm generates SIMD codes based on the data reorganization graph, addressing realistic issues such as runtime alignments, unknown loop bounds, residue iteration counts, and multiple statements with arbitrary alignment combinations. Beyond generating a valid simdization, a preferred embodiment further improves the quality of the generated codes. Four stream-shift placement policies are disclosed, which minimize the number of data reorganization generated by the alignment handling.

US Patent:

8370575, Feb 5, 2013

Filed:

Sep 7, 2006

Appl. No.:

11/470638

Inventors:

Alexandre E. Eichenberger - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US
Tao Zhang - Atlanta GA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711118, 711207, 711221

Abstract:

Process, cache memory, computer product and system for loading data associated with a requested address in a software cache. The process includes loading address tags associated with a set in a cache directory using a Single Instruction Multiple Data (SIMD) operation, determining a position of the requested address in the set using a SIMD comparison, and determining an actual data value associated with the position of the requested address in the set.

US Patent:

8370817, Feb 5, 2013

Filed:

May 27, 2008

Appl. No.:

12/127491

Inventors:

Alexandre E. Eichenberger - Chappaqua NY, US
John Kevin Patrick O'Brien - South Salem NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45
G06F 15/00

US Classification:

717136, 717140, 717143, 717144, 717151, 717159, 712 3, 712 22

Abstract:

A mechanism is provided for optimizing scalar code executed on a single instruction multiple data (SIMD) engine by aligning the slots of SIMD registers. With the mechanism, a compiler is provided that parses source code and, for each statement in the program, generates an expression tree. The compiler inspects all storage inputs to scalar operations in the expression tree to determine their alignment in the SIMD registers. This alignment is propagated up the expression tree from the leaves. When the alignments of two operands in the expression tree are the same, the resulting alignment is the shared value. When the alignments of two operands in the expression tree are different, one operand is shifted. For shifted operands, a shift operation is inserted in the expression tree. The executable code is then generated for the expression tree and shifts are inserted where indicated.