John Raymond Phipps

US Patent:

56311877, May 20, 1997

Filed:

Jan 31, 1994

Appl. No.:

8/188975

Inventors:

John P. Phipps - Phoenix AZ
Stephen P. Robb - Tempe AZ
Judy L. Sutor - Chandler AZ
Lewis E. Terry - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2170

US Classification:

438237

Abstract:

A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

US Patent:

53811054, Jan 10, 1995

Filed:

Feb 12, 1993

Appl. No.:

8/017159

Inventors:

John P. Phipps - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G01R 104

US Classification:

324765

Abstract:

Testing of a semiconductor device (10, 30) is facilitated by forming the semiconductor device (10, 30) to have a first portion (17) that is electrically isolated from a second portion (19, 27). Testing is first performed on the first portion (17) of the semiconductor device (10, 30). After the testing is complete, the first portion (17) of the semiconductor device (10, 30) is electrically coupled to the second portion (19, 27) of the semiconductor device (10, 30).

US Patent:

53650999, Nov 15, 1994

Filed:

Feb 25, 1994

Appl. No.:

8/202856

Inventors:

John P. Phipps - Phoenix AZ
Stephen P. Robb - Tempe AZ
Judy L. Sutor - Chandler AZ
Lewis E. Terry - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2910

US Classification:

257328

Abstract:

A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

US Patent:

44195869, Dec 6, 1983

Filed:

Aug 27, 1981

Appl. No.:

6/296756

Inventors:

John P. Phipps - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G02B 2700

US Classification:

250551

Abstract:

An improved solid state relay and regulator having reduced turn-off time, analog or digital input, and analog or digital output, is obtained by using a depletion JFET as a variable resistance discharge path for a gate of a power MOSFET switching device wherein the gate is charged by a first set of photovoltaic cells optically coupled to but electrically isolated from an LED input. A second set of photovoltaic cells responsive to the same or a separate LED input hold the JFET in an Off state while the MOSFET gate is energized. Variable output and AND logic are obtained.

US Patent:

51153696, May 19, 1992

Filed:

Jan 7, 1991

Appl. No.:

7/637719

Inventors:

Stephen P. Robb - Tempe AZ
John P. Phipps - Phoenix AZ
Michael D. Gadberry - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H02H 902
H03K 1708
G05F 163

US Classification:

361 93

Abstract:

A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is coupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

US Patent:

50050613, Apr 2, 1991

Filed:

Feb 5, 1990

Appl. No.:

7/474889

Inventors:

Stephen P. Robb - Tempe AZ
John P. Phipps - Phoenix AZ
Michael D. Gadberry - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2980
H01L 2906
H01L 2910
H01L 2702

US Classification:

357 2313

Abstract:

A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is copupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

US Patent:

52668312, Nov 30, 1993

Filed:

Nov 12, 1991

Appl. No.:

7/790795

Inventors:

John P. Phipps - Phoenix AZ
Stephen P. Robb - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2104
H01L 2360

US Classification:

257620

Abstract:

A semiconductor structure having an edge termination feature wherein at least one guard ring is disposed in a substrate between a main device portion and the edge of the substrate. A dielectric layer is then disposed on the substrate and a plurality of diodes are disposed on the dielectric layer above the at least one guard ring. The at least one guard ring and the diodes are electrically coupled so that the potential of the guard rings may be fixed by the diodes and leakage is greatly reduced.